Cache Registers; Global Control Register (Icgc); I-Cache Global Control Register (Icgc); Summary Of The I-Cache Registers - Texas Instruments TMS320VC5501 Instruction Cache

I-Cache Registers
6 I-Cache Registers
Table 3.

Summary of the I-Cache Registers

Name
ICGC
ICFARL
ICFARH
ICWMC
6.1

Global Control Register (ICGC)

Figure 6.

I-Cache Global Control Register (ICGC)

15 13 12
Reserved
FLUSHLINE
R-110 R/W-0
Legend: R = Read; W = Write; -n = Value after reset
22 Instruction Cache
Control of the I-Cache is maintained through a set of registers within the
I-Cache. These registers are accessible at addresses in the I/O space of the
DSP. For the addresses, see the TMS320C5501 Fixed-Point Digital Signal
Processor Data Manual (SPRS206) or the TMS320C5502 Fixed-Point Digital
Signal Processor Data Manual (SPRS166).
Description
Global control register
Flush line low address register
Flush line high address register
Way miss-counter register
The TMS320C5501/5502 I-Cache supports one 2-way cache. Before
enabling the I-Cache, use the global control register (ICGC) to initialize it.
You can write two legal values to ICGC:
CE3Ch to initialize the I-Cache
-
DE3Ch to force a line flush
-
Do not write other values to this register. A DSP reset invalidates the content
of ICGC. Make sure your initialization code writes CE3Ch to ICGC after every
reset.
11
Reserved
R/W-011000111100
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