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3.13.9 Video Capture Channel x Event Count Register (VCxEVTCT)
The video capture channel x event count register (VCxEVTCT) is programmed with the number of EDMA
events to be generated for each capture field.
An event counter tracks how many events have been generated and indicates which threshold value
(VCTHRLD1 or VCTHRLD2 in VCxTHRLD) to use in event generation and in the outgoing data counter.
Once the CAPEVTCTn number of events have been generated, the EDMA logic switches to the other
threshold value. See
The video capture channel x event count register (VCxEVTCT) is shown in
Table
3-22.
Figure 3-29. Video Capture Channel x Event Count Register (VCxEVTCT)
31
28
Reserved
R-0
15
12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-22. Video Capture Channel x Event Count Register (VCxEVTCT) Field Descriptions
(1)
Bit
field
symval
31-28 Reserved
-
27-16 CAPEVTCT2
OF(value)
DEFAULT
15-12 Reserved
-
11-0
CAPEVTCT1
OF(value)
DEFAULT
(1)
For CSL implementation, use the notation VP_VCxEVTCT_CAPEVTCTn_symval
3.13.10 Video Capture Channel B Control Register (VCBCTL)
Video capture is controlled by the video capture channel B control register (VCBCTL) shown in
Figure 3-30
and described in
SPRUEM1 – May 2007
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Section
2.3.1.
27
11
(1)
Value
BT.656 or Y/C Mode
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
0-FFFh
Number of EDMA event sets
(YEVT, CbEVT, CrEVT) to be
generated for field 2 capture.
0
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
0-FFFh
Number of EDMA event sets
(YEVT, CbEVT, CrEVT) to be
generated for field 1 capture.
0
Table
3-23.
Figure 3-29
CAPEVTCT2
R/W-0
CAPEVTCT1
R/W-0
Description
Raw Data Mode
Not used.
Not used.
Video Capture Registers
and described in
16
0
TCI Mode
Not used.
Not used.
Video Capture Port
81
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