Clock, Qualifier, And Data Inputs Test 4 - HP 1652B Getting Started Manual

Clock, Qualifier,
Description:
and Data Inputs
Test 5
This performance test verifies the maximum clock rate for mixed mode clocking
during a state operation.
Specification:
Clock repetition rate:
Single phase is 35 MHz maximum (25 MHz maximum for
the HP 1653B). With time or state counting, minimum time between states is 60
ns (16.7 MHz maximum). Both mixed and demultiplexed clocking use master-slave
clock timing. The master clock must follow the slave clock by at least
10
ns and
precede the next slave clock by 50 ns.
Equipment Required:
Pulse Generator .......................... HP
816lA/O20
Oscilloscope ............................ HP
54502A
50
Ohm Feedthrough
(2)
................... HP
IOIOOC
Test Connector
(2)
........................ see figure 3-1 and
3-2
BNC m-m Coupler
(2)
..................... HP
1250-0216
BNC Cable
(2)
........................... HP 10503A
BNCTee m-f-f (2) ......................... HP
1250-0781
Procedure:
1. Connect the HP 1652B/1653B and test equipment as in figure 3-22 by
connecting channels O-3 and 8-11 of the pod under test to the test connector.
On the slave clock transition, the four bits of the lower byte are transferred to
the logic analyzer. On the master clock transition, the four bits of the upper
byte are transferred to the logic analyzer.
LOGIC ANALYZER
FIGURE
3-l
CLK BIT
1
P
DATA BITS ;
PO
D
/
r
500
/ a
I
DATA
FIGURE '
3-1
GND
*
01650849
Figure
3-22.
Setup for Data Test 5
I
Note m
In
this setup, only eight channels are tested at one time to minimize loading. The
ground lead must be connected to ensure accurate test results.
HP 1652B/16538
Performance Tests
Service Manual
3-21