HP 1652B Getting Started Manual page 314

[IWHINE 1 I- Timing
Fomt
Specification
Pod 3
Pod 2 Pod 1
I TTL
I I
TTL
1 I
TTL
I
Rctivl ty ) ----------------
---------------- ----------------
Label
Pol 15 . . . . 87 .,.. 0 15 . . . . 87 . . . . 0 15 . . . . 87 . . . . 0
q
1 ********CM***+*+ $1 ,1 I I 1. , ******+ ***,,,***,,,*I*,
t
t
t
t
Bit 31 Bit 19 Bit 8 Bit 0
Figure
17-4.
Numbering of Assigned Bits
Pod Threshold
Each pod has a threshold level assigned to it. For the HP 1653B Logic
Analyzer, threshold levels may be defined for Pods 1 and 2 individually.
For the HP 1652B Logic Analyzer, threshold levels may be defined for
Pods
1,2
and 3 individually, and one threshold for Pods
4
and 5. It does
not matter if Pods 4 and 5 are assigned to different analyzers. Changing
the threshold of one will change the threshold of the other.
If you place the cursor on one of the pod threshold fields and press
SELECT, you will see the following pop-up menu.
Figure 17-5. Pod Threshold Pop-Up Menu
TTL sets the threshold at + 1.6 volts, and ECL sets the threshold at
- 1.3
volts.
The User-defined option lets you set the threshold to a specific voltage
between -9.9 V and + 9.9 V. If you select this option you will see a
Numeric Entry pop-up menu as shown.
Figure 17-6. User-Defined Numeric Entry Pop-Up Menu
Timing Format Specification Menu
HP
16528/16538
17-6
Front-Panel Reference