Clock Inputs Display; Pod Clock Field (State Only) - HP 1660CP Series User Manual

Logic analyzers
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Clock Inputs Display

Beneath the Clock Inputs display, and next to the activity indicators, is a
group of all clock inputs available in the present configuration. The number
of available clocks depends on the model. The J and K clocks appear with pod
pair 1/2, the L and M with pod pair 3/4, and N and P with pod pairs 7/8 for the
HP 1660 and 5/6 for the HP 1661. In a model with more than three pod pairs,
all other clock lines are displayed to the left of the displayed master clocks,
and are used only as data channels.
With the exception of the Range resource, all unused clock bits can be used
as data channels in the trigger terms. Activity indicators above the clock
identifier show clock or data signal activity.
Pod clock
Clock inputs
Pod Clocks

Pod clock field (State only)

The pod clock field identifies the type of clock arrangement assigned to each
pod. When the pod clock field is selected, a clock arrangement menu appears
with the choices of Master, Slave, or Demultiplex. Once a pod clock is
assigned a clock arrangement, its identity and function follows what is
configured in the Master and Slave Clock fields.
The Analyzer Format Menu
Clock Inputs Display
8-35

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