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When in the "edge trigger" mode, the preamp outputs are fed through a high speed
voltage comparator using a reference voltage from the DAC.
Oscilloscope
Theory of
Operation
Attenuator/
Preamps
Post Amplifier
ADC and FISO
Memory
Triggering
The oscilloscope circuitry provides the conditioning,
sampling, digitizing, and
storage of the signals at the channel input connectors. The channels are identical.
The trigger circuitry input can be selected between the oscilloscope channels and
the logic analyzer. A 400 MHz oscillator, with the time base and mux/sync
(multiplexer
synchronizer), provides the sample clocking. After conditioning,
the
signals are digitized and stored in a hybrid IC containing both the ADC and
memory. The signal data is then transferred over the data bus where it is
processed for display.
The channel signals are conditioned by the attenuator/preamps,
thick film hybrids
containing passive attenuators, impedance converters, and a programmable
amplifier.
The channel sensitivity defaults to the standard
l-2-5
sequence (other
sensitivities can be set also). However, the firmware uses passive attenuation of 1,
$25, and 125, with the programmable
preamp, to cover the entire sensitivity range.
The input has a selectable 1 MQ or 50 Q input impedance.
Compensation
for the
passive attenuators is laser trimmed and not adjustable.
After the passive
attenuators, the signal is split into high-frequency
and low-frequency components.
Low frequency components are amplified on the PC board where they are
combined with the offset voltage.
The high- and low-frequency components of the signal are recombined and
applied to the input FET of the preamp. The FET provides a high input
impedance for the preamp. The programmable
preamp adjusts the gain to suit the
required sensitivity and provides two output signals. One signal is the same
polarity as the input and goes to the trigger circuitry.
The other is of the opposite
polarity and is sent to the post amplifier.
The post amplifier conditions the signal for the ADC. It has a gain of
approximately
2.5 and it has one compensation capacitor adjustment per channel.
This adjustment effects the transition rise time and overshoot.
A
single hybrid digitizes and stores the channel signal. Digitization
is done by a set
of comparators in a flash converter. A precision voltage divider within the ADC
provides a separate reference for each comparator.
This voltage divider is
controlled by a reference supply and amplifier on the PC board.
The FISO (fast in, slow out) memory is 2 k by 6-bit bytes. Sample clocks are
provided by the time base circuitry.
At
500 ns/div and faster, the sample clock is
400 MHz.
At
sweep speeds of
1
us and slower, the sample clocks range from 200
MHz to 25 Hz. The FISO data is buffered onto the CPU data bus for further
processing.
The trigger circuitry accepts inputs from both oscilloscope channels, the logic
analyzer, and the time base. Only one of these signals is multiplexed
into the
trigger circuitry, depending on the trigger mode. For example, the input from the
time base is used while the instrument is in the "trigger immediate"
mode.
HP 16528/1653B
Theory
of Operation
Service
Manual
6A-9
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