To Test The Single-Clock, Single-Edge, State Acquisition - HP 16555A Service Manual

To test the single-clock, single-edge, state acquisition

Testing the single-clock, single-edge, state acquisition verifies the performance of the
following specifications:
•
Minimum master to master clock time.
•
Maximum state acquisition speed.
•
Setup/Hold time.
•
Minimum clock pulse width.
Multicard modules must be reconfigured as one-card modules for this test.
This test checks a combination of data channels using a single-edge clock at three
selected setup/hold times.
Equipment Required
Equipment
Pulse Generator
Digitizing Oscilloscope
Adapter
SMA Coax Cable (Qty 3)
Coupler (Qty 3)
BNC Test Connector, 6x2 (Qty 3)
Set up the equipment
Turn on the equipment required and the logic analyzer. Let them warm up for
1
30 minutes before beginning the test if you have not already done so.
Set up the pulse generator according to the following table.
2
Pulse Generator Setup
Channel 1
Delay: 0 ps
Width: 3.5 ns
High: -0.9 V
Low: -1.7 V
COMP: Disabled
(LED off)
* If running HP 16500B mainframe software version v2.xx on an HP 16555A, set Channel 2 Doub: 10 ns, and Period to 20 ns.
110-MHz single-clock state acquisition mode is available with HP 16500B mainframe operating system v3.00 or higher or
HP 16500C mainframe operating system v1.00 or higher. For information on software version, refer to "Operating System" in
chapter 1.
3–18
Critical Specifications
110 MHz 3.5 ns pulse width, <600 ps rise time
≥ 6 GHz bandwidth, <58 ps rise time
SMA(m)-BNC(f)
BNC(m-m)
Channel 2
Doub: 9.05 ns *
Width: 3.5 ns
High: -0.9 V
Low: -1.7 V
COMP: Disabled
(LED off)
Recommended
Model/Part
HP 8131A option 020
HP 54750A w/ HP 54751A
HP 1250-1200
HP 8120-4948
HP 1250-0216
Period
18.1 ns *