Fec - GE LOGIQ 5 PRO Service Manual

GE M S
EDICAL YSTEMS
D 2380207, R
IRECTION EVISION
5-4-5-1 Overview (cont'd)
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5-4-6

FEC

FEC ASSY
5-4-6-1 Overview
• CHAF:
Three CHAFs have functions of coded excitation decorder and 2nd harmonic filter.
• BIPC and RIF:
Have functions of RF memory controller.
The RIF mainly controls RF memory data bus, RF data flow pass, and RF gain.
The BIPC, which is interface of JUSC bus, mainly controls CHAF and RF memory address bus.
• COMSO:
Has functions of detector, B/M mode edge enhance, Log compression, and dynamic range control.
• PCI IF:
Converts JUSC bus in FEC board. The local bus is connected to each block. It transfers B/M mode
data to PACO FPGA via the COMSO data bus.
• USC IF:
Has functions of generation to JUSC bus, generation of TGC signal and test signal for self-
diagnostics, COMSO control.
7
Reference Voltage Generator : This mode is for imaging. The parameters specific to scan line
number are sent to OQCARDs and the start trigger for receiving signals is generated.
Access Mode:
This mode is for accessing flash memories and OQCARDs.
Control
ADDER
Harmonic Filter
JUSC
CONTROL
Scan Control
PCI I/F for SH-4
HV
JUSC Power
Control
Check
BUS
Figure 5-10 FEC Block Diagram
Chapter 5 Components and Functions (Theory)
COMSO
SH-4
for
Memory
Memory
PGC, Test Sig
Gen
LOGIQ™5 PRO S
ERVICE
Memory
16 MB
Data
Line Buffer
&
Memory
Controller
I960
for
PCI I/F
Clock Gen, Circuit
M
ANUAL
5-11