Rds - GE LOGIQ 5 PRO Service Manual

GE M S
EDICAL YSTEMS
D 2380207, R
IRECTION EVISION
5-4-5

RDS

5-4-5-1 Overview
Channel 0
Channel 7
Channel 8
Channel 15
Channel 16
Channel 23
Channel 24
Channel 31
The RDS sub-system is the receive beam former and consist of 2 RDS assys. Each RDS assy have
capability of 32 channels digital receive beamforming. The each digital beamforming output data of the
RDS assy are sent to FEC. FEC add each other and makes final 64 channel beamforming data
Delay control data for receive beamforming are contained in Flash memory. Typically 2 or 3 probes data
are saved in flash memory. If new probe is connected, additional probe data will be downloaded from
HDD in BEP to Flash memory
Main items are
-
-
-
5-10
7
12 Bits
BUF BUF
ADC
x 8
12 Bits
BUF BUF
ADC
12 Bits
BUF BUF
ADC
x 8
12 Bits
BUF BUF
ADC
12 Bits
BUF BUF
ADC
x 8
12 Bits
BUF BUF
ADC
12 Bits
BUF BUF
ADC
x 8
12 Bits
BUF BUF
ADC
Figure 5-9 RDS Block Diagram
BICTOP FPGA : Provide interfaces with FEC through JUSC Bus. This fpga control all
OQCARD asic for receive beamforming. All of parameter information for asic operation are
loaded into OQCARD asic from FEC through this fpga.
OQCARD :Digital receive beamforming ASIC. Each OQCARD have capability of 8 channel
receiving data inputs. Each input data can be 12 bits. Operation clock is 40 MHz. 4 OQCARD
asics are used in a RDS board and each OQCARD summing data output are cascaded to next
OQCARD asic. So the last summing output of the last OQCARD are transferred to FEC for
adding two summing data of each RDS board. The receive beamforming control logic in
OQCARD asic need delay information data for each channel's control logic. This delay
information data are downloaded into asic from flash memory by BICTOP fpga.
Flash Memory : Flash memory keep the receive delay data for OQCARD asic. During scan
time, these data are downloaded into OQCARD asic by fpga. Memory capacity is 8MBytes
each board, typically 2 or 3 probes data.
Section 5-4 - Front End
OQCARD
OQCARD
OQCARD
8M Byte FLASH
for RX Delay
OQCARD
Test
Signal
Buffer
Reference
Voltage
Generator
LOGIQ™5 PRO S
BIC
JUSC BUS
FPGA
To FEC
Test Sig.
From FEC
M
ERVICE ANUAL