Merge And Logical - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual

4.6.6

Merge and Logical

40
F9
fmerge.s
fmerge.ns
fmerge.se
fmix.lr
fmix.r
fmix.l
fsxt.r
fsxt.l
fpack
fswap
fswap.nl
fswap.nr
fand
fandcm
for
fxor
fpmerge.s
fpmerge.ns
fpmerge.se
4.6.7 Conversion
4.6.7.1 Convert Floating-point to Fixed-point
40
F10
Instruction
fcvt.fx.sf
fcvt.fxu.sf
fcvt.fx.trunc.sf
fcvt.fxu.trunc.sf
fpcvt.fx.sf
fpcvt.fxu.sf
fpcvt.fx.trunc.sf
fpcvt.fxu.trunc.sf
Volume 3: Instruction Formats
37 36 34 33 32
0 - 1 x x
6
4 3 1 6
Instruction
f = f
1 2
37 36 35 34 33 32
0 - 1 sf x x
6
4 1 2 1 6
Operands
f = f
1 2
27 26 20 19
f
3
7
Operands Opcode
0
, f
3
1
27 26 20 19
7
Opcode
x
0
0
1
13 12 6 5
f f
2 1
7 7
Extension
x x
10
11
12
39
3A
3B
3C
3D
28
0 34
35
36
2C
2D
2E
2F
10
11
12
13 12 6 5
f f
2 1
7 7
Extension
x sf
6
18
19
1A
1B
See Table 4-63 on
page 3:358
18
19
1A
1B
0
qp
6
6
0
qp
6
3:363