Protected Mode Exceptions; Real-Address Mode Exceptions; Virtual-8086 Mode Exceptions; Exception Mnemonics, Names, And Vector Numbers - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 4 REV 2.3 Manual

2.2.5

Protected Mode Exceptions

The "Protected Mode Exceptions" section lists the exceptions that can occur when the
instruction is executed in protected mode and the reasons for the exceptions. Each
exception is given a mnemonic that consists of a pound sign (#) followed by two letters
and an optional error code in parentheses. For example, #GP(0) denotes a general
protection exception with an error code of 0.
mnemonic with the corresponding interrupt vector number and exception name. See
Chapter 5, Interrupt and Exception Handling, in the Intel Architecture Software
Developer's Manual, Volume 3, for a detailed description of the exceptions.
Application programmers should consult the documentation provided with their
operating systems to determine the actions taken when exceptions occur.
2.2.6

Real-address Mode Exceptions

The "Real-Address Mode Exceptions" section lists the exceptions that can occur when
the instruction is executed in real-address mode.
Table 2-2.
Vector
No.
0
1
3
4
5
6
7
8
10
11
12
13
14
16
17
18
a. The UD2 instruction was introduced in the Pentium
b. This exception was introduced in the Intel
c. This exception was introduced in the Pentium processor and enhanced in the Pentium Pro processor.
2.2.7

Virtual-8086 Mode Exceptions

The "Virtual-8086 Mode Exceptions" section lists the exceptions that can occur when
the instruction is executed in virtual-8086 mode.
Volume 4: Base IA-32 Instruction Reference

Exception Mnemonics, Names, and Vector Numbers

Mnemonic
#DE Divide Error
#DB Debug
#BP Breakpoint
#OF Overflow
#BR BOUND Range Exceeded
#UD Invalid Opcode (Undefined Opcode)
#NM Device Not Available (No Math
Coprocessor)
#DF Double Fault
#TS Invalid TSS
#NP Segment Not Present
#SS Stack Segment Fault
#GP General Protection
#PF Page Fault
#MF Floating-point Error (Math Fault)
#AC Alignment Check
#MC Machine Check
Table 2-2
Name
DIV and IDIV instructions.
Any code or data reference.
INT 3 instruction.
INTO instruction.
BOUND instruction.
UD2 instruction or reserved opcode.
Floating-point or WAIT/FWAIT instruction.
Any instruction that can generate an
exception, an NMI, or an INTR.
Task switch or TSS access.
Loading segment registers or accessing
system segments.
Stack operations and SS register loads.
Any memory reference and other protection
checks.
Any memory reference.
Floating-point or WAIT/FWAIT instruction.
Any data reference in memory.
Model dependent.
®
Pro processor.
®
486 processor.
associates each two-letter
Source
b
c
a
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