Miscellaneous M-Unit Instructions - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual
Architecture software developer's manual revision 2.3
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4.4.9
Miscellaneous M-Unit Instructions
The miscellaneous M-unit instructions are encoded in major opcode 0 along with the
system/memory management instructions. See
page 3:345
4.4.9.1
Allocate Register Stack Frame
40
M34
Instruction
f
alloc
Note: The three immediates in the instruction encoding are formed from the operands
as follows:
sof =
sol =
sor =
4.4.9.2
Move to PSR
40
M35
Instruction
p
mov
mov
4.4.9.3
Move from PSR
40
M36
Instruction
p
mov
mov
4.4.9.4
Break (M-Unit)
40
M37
Instruction
break.m
3:344
for a summary of the opcode extensions.
37 36 35
33 32 31 30
27 26
1
x
sor
3
4
1
3
2
4
Operands
r
= ar.pfs, i, l, o, r
1
+
+
i
l
o
+
i
l
>> 3
r
37 36 35
33 32
27 26
1
x
x
3
6
4
1
3
6
Operands
psr.l = r
2
psr.um = r
2
37 36 35
33 32
27 26
1
x
x
3
6
4
1
3
6
Operands
r
= psr
1
r
= psr.um
1
37 36 35
33 32 31 30
27 26 25
0
i
x
x
x
3
2
4
4
1
3
2
4
Operands
imm
21
"System/Memory Management" on
20 19
sol
sof
7
7
Opcode
1
20 19
r
2
7
7
Opcode
1
14
Opcode
1
imm
20a
1
20
Opcode
x
0
0
13 12
6 5
r
1
7
Extension
x
3
6
13 12
6 5
7
Extension
x
x
3
6
2D
0
29
13 12
6 5
r
1
7
Extension
x
x
3
6
25
0
21
6 5
Extension
x
x
3
4
2
0
0
Volume 3: Instruction Formats
0
qp
6
0
qp
6
0
qp
6
0
qp
6
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