Lftype Mnemonic Values - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual

lfetch
lfetch — Line Prefetch
(qp) lfetch.lftype.lfhint [r
Format:
( ) lfetch.
qp
( ) lfetch.
qp
( ) lfetch.
qp
( ) lfetch.
qp
( ) lfetch.
qp
The line containing the address specified by the value in GR
Description:
level of the data memory hierarchy. The value of the lfhint modifier specifies the locality
of the memory access; see
details. The mnemonic values of lfhint are given in
The behavior of the memory read is also determined by the memory attribute
associated with the accessed page. See
Volume 2. Line size is implementation dependent but must be a power of two greater
than or equal to 32 bytes. In the exclusive form, the cache line is allowed to be marked
in an exclusive state. This qualifier is used when the program expects soon to modify a
location in that line. If the memory attribute for the page containing the line is not
cacheable, then no reference is made.
The completer,
associated with a regular load.
Table 2-37.
lftype Mnemonic
In the base update forms, after being used to address memory, the value in GR
incremented by either the sign-extended value in
or the value in GR
the NaT bit corresponding to GR
– no fault is raised.
In the reg_base_update_form and the imm_base_update_form, if the NaT bit
corresponding to GR r
the post-increment acts as a hint to implicitly prefetch the indicated cache line. This
implicit prefetch uses the locality hints specified by lfhint. The implicit prefetch does not
affect program functionality, does not raise any faults, and may be ignored by the
implementation.
In the no_base_update_form, the value in GR r
hint is implied.
If the NaT bit corresponding to GR
the reg_base_update_form and imm_base_update_form, the post increment of GR r
performed and prefetch is hinted as described above.
lfetch instructions, like hardware prefetches, are not orderable operations, i.e., they
have no order with respect to prior or subsequent memory operations.
3:164
]
3
. [ ],
lftype lfhint r r
3 2
. [ ],
lftype lfhint r imm
3 9
.excl. [ ]
lftype lfhint r
3
.excl. [ ],
lftype lfhint r r
3 2
.excl. [ ],
lftype lfhint r imm
3 9
Section 4.4, "Memory Access Instructions" on page 1:57
, specifies whether or not the instruction raises faults normally
lftype
Table 2-37

lftype Mnemonic Values

none No faults are raised
fault Raise faults
(in the reg_base_update_form). In the reg_base_update_form, if
r
2
r
is clear, then the address specified by the value in GR
3
no_base_update_form, exclusive_form
reg_base_update_form, exclusive_form
imm_base_update_form, exclusive_form
Table 2-38.
Chapter 4, "Addressing and Protection" in
defines these two options.
Interpretation
(in the imm_base_update_form)
imm
9
is set, then the NaT bit corresponding to GR
2
is not modified and no implicit prefetch
3
is set then the state of memory is not affected. In
r
3
no_base_update_form
reg_base_update_form
imm_base_update_form
is moved to the highest
r
3
r
3
is set
r
3
after
r
3
Volume 3: Instruction Reference
M18
M20
M22
M18
M20
M22
for
is
is
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