Memory Exchange Size - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual

xchg
xchg — Exchange
( ) xchg
Format: qp sz
A value consisting of sz bytes is read from memory starting at the address specified by
Description:
the value in GR
memory starting at the address specified by the value in GR r
memory is then zero extended and placed in GR r
r is cleared. The values of the sz completer are given in
1
If the address specified by the value in GR
value being accessed in memory, an Unaligned Data Reference fault is taken
independent of the state of the User Mask alignment checking bit, UM.ac (PSR.ac in the
Processor Status Register).
Both read and write access privileges for the referenced page are required.
Table 2-60.
The exchange is performed with acquire semantics, i.e., the memory read/write is
made visible prior to all subsequent data memory accesses. See
"Sequentiality Attribute and Ordering" on page 2:82
The memory read and write are guaranteed to be atomic.
This instruction is only supported to cacheable pages with write-back write policy.
Accesses to NaTPages cause a Data NaT Page Consumption fault. Accesses to pages
with other memory attributes cause an Unsupported Data Reference fault.
The value of the ldhint completer specifies the locality of the memory access. The values
of the ldhint completer are given in
affect program functionality and may be ignored by the implementation. See
Section 4.4.6, "Memory Hierarchy Control and Consistency" on page 1:69
3:274
. = [ ],
ldhint r r r
1 3 2
. The least significant sz bytes of the value in GR r
r
3

Memory Exchange Size

sz Completer
1
2
4
8
and the NaT bit corresponding to GR
1
Table
is not naturally aligned to the size of the
r
3
Bytes Accessed
for details on memory ordering.
Table 2-34 on page 3:152. Locality hints do not
are written to
2
. The value read from
3
2-60.
1 byte
2 bytes
4 bytes
8 bytes
Section 4.4.7,
for details.
Volume 3: Instruction Reference
M16