Unpack High Operation; Unpack Low Operation - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 4 REV 2.3 Manual

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operand is accessed from memory but only the high order 64 bits are utilized by the
instruction.
Figure 4-6.
The UNPCKLPS (Unpacked low packed single-precision floating-point) instruction
performs an interleaved unpack of the low-order data elements of first and second
packed single-precision floating-point operands. It ignores the higher half part of the
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operand is accessed from memory but only the low order 64 bits are utilized by the
instruction.
Figure 4-7.
4.6.1.5 Conversion Instructions
These instructions support packed and scalar conversions between 128-bit SSE
registers and either 64-bit integer MMX technology registers or 32-bit integer IA-32
registers. The packed versions behave identically to original MMX technology
instructions, in the presence of x87-FP instructions, including:
• Transition from x87-FP to MMX technology (TOS=0, FP valid bits set to all valid).
• MMX technology instructions write ones (1's) to the exponent part of the
corresponding x87-FP register.
• Use of EMMS for transition from MMX technology to x87-FP.
Volume 4: IA-32 SSE Instruction Reference
(Figure 4-6). When unpacking from a memory operand, the full 128-bit

Unpack High Operation

X4
Y4
Y4
(Figure 4-7). When unpacking from a memory operand, the full 128-bit

Unpack Low Operation

X4
Y4
Y2
X3 X2
Y3 Y2
X4 Y3
X3 X2
Y3 Y2
X2 Y1
X1
Y1
X3
X1
Y1
X1
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