Operating On Nans - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 4 REV 2.3 Manual

4.7.1.9 Indefinite
In response to a masked invalid-operation floating-point exceptions, the indefinite
value QNAN is produced. The integer indefinite, which can be produced during
conversion from single-precision floating-point to 32-bit integer, is defined to be
80000000H.
4.7.2

Operating on NaNs

As was described in
supports two types of NaNs: SNaNs and QNaNs. An SNaN is any NaN value with its
most-significant fraction bit set to 0 and at least one other fraction bit set to 1. (If all
the fraction bits are set to 0, the value is an .) A QNaN is any NaN value with the
most-significant fraction bit set to 1. The sign bit of a NaN is not interpreted.
As a general rule, when a QNaN is used in one or more arithmetic floating-point
instructions, it is allowed to propagate through a computation. An SNaN on the other
hand causes a floating-point invalid-operation exception to be signaled. SNaNs are
typically used to trap or invoke an exception handler.
The invalid operation exception has a flag and a mask bit associated with it in MXCSR.
The mask bit determines how the an SNaN value is handled. If the invalid operation
mask bit is set, the SNaN is converted to a QNaN by setting the most-significant
fraction bit of the value to 1. The result is then stored in the destination operand and
the invalid operation flag is set. If the invalid operation mask is clear, an invalid
operation fault is signaled and no result is stored in the destination operand.
When a real operation or exception delivers a QNaN result, the value of the result
depends on the source operands, as shown in
described in
NaN for these instructions, the Src2 operand (either NaN or real value) is written to the
result; this differs from the behavior for other instructions as defined in
which is to always write the NaN to the result, regardless of which source operand
contains the NaN. This approach for MINPS/MAXPS allows NaN data to be screened out
of the bounds-checking portion of an algorithm. If instead of this behavior, it is required
that the NaN source operand be returned, the min/max functionality can be emulated
using a sequence of instructions: comparison followed by AND, ANDN and OR.
In general Src1 and Src2 relate to an SSE instruction as follows:
Except for the rules given at the beginning of this section for encoding SNaNs and
QNaNs, software is free to use the bits in the significand of a NaN for any purpose. Both
SNaNs and QNaNs can be encoded to carry and store data, such as diagnostic
information.
4:480
Section 4.7.1.8, "NaNs" on page
Table 4-3 are the MINPS and MAXPS instructions. If only one source is a
ADDPS Src1, Src2/m128
4:479, the Intel SSE architecture
Table 4-3. The exceptions to the behavior
Volume 4: IA-32 SSE Instruction Reference
Table 4-3,