Feature Flags Returned In Edx Register - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 4 REV 2.3 Manual

CPUID—CPU Identification (Continued)
When the input value in EAX is 1, three unrelated pieces of information are returned to
the EBX register:
• Brand index (low byte of EBX)
table that contains brand strings for IA-32 processors. Please refer to AP-485,
Intel
for information on brand indices.
Note: The Brand index field is not supported for processors based on Itanium
• CLFLUSH instruction cache line size (second byte of EBX)
the size of the cache line flushed with CLFLUSH instruction in 8-byte increments.
This field is valid only when the CLFSH feature flag is set.
• Local APIC ID (high byte of EBX)
the local APIC on the processor during power up.
Note: The local APIC ID field is invalid for processors based on the Itanium
When the EAX register contains a value of 1, the CPUID instruction (in addition to
loading the processor signature in the EAX register) loads the EDX register with the
feature flags. The feature flags (when a Flag = 1) indicate what features the processor
supports.
A feature flag set to 1 indicates the corresponding feature is supported. Software
should identify Intel as the vendor to properly interpret the feature flags.
Table 2-5.
Bit
0
1
2
3
4
5
4:80
®
Processor Identification and the CPUID Instruction (Order Number 241618)
architecture, zero (unsupported encoding) is returned.
architecture, reserved value is returned. Software should check the
feature flags to make sure they are not running on processors based on
the Itanium architecture before interpreting the return value in this
field.
Table 2-5 lists the currently defined feature flag values.

Feature Flags Returned in EDX Register

Mnemonic
FPU
VME
DE
PSE
TSC
MSR
this number provides an entry into a brand string
–
this number is the 8-bit ID that is assigned to
–
Floating Point Unit On-Chip. The processor contains an x87 FPU.
Virtual 8086 Mode Enhancements. Virtual 8086 mode
enhancements, including CR4.VME for controlling the feature,
CR4.PVI for protected mode virtual interrupts, software interrupt
indirection, expansion of the TSS with the software indirection bitmap,
and EFLAGS.VIF and EFLAGS.VIP flags.
Debugging Extensions. Support for I/O breakpoints, including
CR4.DE for controlling the feature, and optional trapping of accesses
to DR4 and DR5.
Page Size Extension. Large pages of size 4Mbyte are supported,
including CR4.PSE for controlling the feature, the defined dirty bit in
PDE (Page Directory Entries), optional reserved bit trapping in CR3,
PDEs, and PTEs.
Time Stamp Counter. The RDTSC instruction is supported, including
CR4.TSD for controlling privilege.
Model Specific Registers RDMSR and WRMSR Instructions. The
RDMSR and WRMSR instructions are supported. Some of the MSRs
are implementation dependent.
Volume 4: Base IA-32 Instruction Reference
this number indicates
–
Description