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This chapter describes functionality of the Cyclone Evaluation Platform's subsystems. Section 4.4, I/O INTERFACE
describes the general I/O implementation. Subsections further describe each functional block. Section 4.5, DRAM
SUBSYSTEM similarly defines the DRAM implementation. Also covered are Clock Generation, Reset, Interrupt and
Ready Logic.
4.1
FUNCTIONAL OVERVIEW
As shown in Figure 1-1, Cyclone EP and PCI-SDK Platform Functional Block Diagram (pg. 1-1), the
main functional blocks and features include:
•
High-performance interleaved DRAM subsystem:
— Operates at 2-0-0-0 wait states for burst reads.
— DRAM subsystem is expandable up to 32 Mbytes.
•
I/O subsystem provides data buffers and simplified control:
— Supports FLASH from 256 Kbit to 2 Mbit and FLASH, an 8-bit memory, is used
for the monitor and start-up diagnostics.
— The Centronics-compatible parallel port allows fast download of code or data to
the Cyclone EP.
— The asynchronous serial (RS-232) port provides transfers up to 115.2 KBaud.
— An Z8536 timer/counter provides three 16 bit counters, with interrupts.
•
An expansion bus (Squall II Module) allows expansion cards and external devices direct access
to the i960
4.2
CLOCK GENERATION
The Cyclone EP's clocking section must handle the clocking requirements of the various i960
processors. The clock generation circuit is based on an AV9155-01 device which generates a 2x and 1x
processor clock based on the FREQ(2:0) switches on the CPU module. The AV9155-0 also generates
the 1.843 MHz baud rate clock and a 16 MHz clock. The 16 MHz clock is later divided to 4 MHz and
used for the counter/timers and DRAM refresh generation.
Clock distribution is performed by an CY7BB991-7 device with an internal PLL. Output clocks from
this device are distributed back to the CPU module, Squall II Module, and on-board logic. This device
guarantees a maximum skew of ±250 ps between outputs, and ±500 ps between the input and the
outputs. Therefore, all clocks on the board are within ±1 ns, making the design work very straight-
forward. All clock signals are terminated with 22 ohm series resistors.
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processor's bus and control signals.
CHAPTER 4
THEORY OF OPERATION
4-1
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