Register Maps; Scv64; Table 6: Scv64 Register Map - Performance Computer PT-VME161 User Manual

Register Maps

The "INIT" column in the register map descriptions below identify the initial register values typically
programmed by PTI for our applications. All "INIT" values are in hexadecimal, registers that are "don't
care" at initialization time contain a hyphen.

SCV64

See "APPENDIX H: PT-VME151A Differences From VME131/141" on page 94 for in-depth discus-
sion of initialization issues. See APPENDIX I: and APPENDIX J: for more information.

Table 6: SCV64 Register Map

ADDRESS REGISTER
18000000h DMALAR
18000004h DMAVAR
18000008h DMATC
1800000Ch DCSR
18000010h VMEBAR
18000014h RXDATA
18000018h RXADDR
1800001Ch RXCTL
18000020h BUSSEL
18000024h IVECT
18000028h APBR
1800002Ch TXDATA
18000030h TXADDR
18000034h TXCTRL
18000038h LMFIFO
1800003Ch MODE
18000040h SA64BAR
18000044h MA64MAR
18000048h LAG
1800004Ch DMAVTC
18000050h -
1800007Fh
18000080h STAT0
18000084h STAT1
18000088h GENCTL
Extensible Single Board Computer/Controller User's Manual 69
FUNCTION
DMA Local Address Register
DMA VMEbus Address Register
DMA Transfer Count
Control and Status Register
VMEbus Slave Base Address Register
Receive FIFO Data bits output latch
Receive FIFO Address bits output
latch
Receive FIFO Control bits output latch
VMEbus Select
VMEbus Interrupt Vector
Access Protect Boundary
Transmit FIFO Data bits output latch
Transmit FIFO Address bits output
latch
Transmit FIFO Control bits output
latch
Location Monitor FIFO read port
SCV64 Mode Control
Slave A64 Base Address Register
Master A64 Base Address Register
Local Address Generator
DMA VMEbus Transfer Count
RESERVED
Status Register 0
Status Register 1
General Control Register
Performance Computer
INIT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1C