Duart Interrupt Request (-Intp<5>); Vmebus Interrupts; Interrupt Acknowledgment; Vmebus Requester - Performance Computer PT-VME161 User Manual

The 4AV bit in the SCV64 Local Interrupts 5 and 4 Control Register determines whether a
"vectored" or "auto-vectored" interrupt is presented to the 68060. The EPAK [-EPVIR]
signal drives the SCV64 interrupt input pin -LIRQ4 through signal line [-INTP<4>].
!
CAUTION: Due to the PT-VME161 hardware implementation the "vectored" option must
always be used for the SCV64 Local Interrupts 5 and 4 Control Register 4AV bit.
DUART Interrupt Request (-INTP<5>)
This interrupt is driven by the DUART Interrupt Request signal. When the 68060 acknowl-
edges the interrupt the SCV64 asserts an interrupt acknowledge (-INTA<5>) back to the
DUART. The interrupt request is negated by servicing the appropriate interrupt source in
the DUART.
The interrupt is enabled by setting the L5E bit in the SCV64 Local Interrupt Enable
Register. The current state of this signal can be read in the LI5 status bit of the SCV64 Local
Interrupt Status Register. The interrupt request level presented to the 68060 is determined
by 5L2, 5L1, and 5L0 control bits in the SCV64 Local Interrupts 5 and 4 Control Register.
The 5AV bit in the SCV64 Local Interrupts 5 and 4 Control Register determines whether a
"vectored" or "auto-vectored" interrupt is presented to the 68060. The DUART IRQ pin
drives the SCV64 interrupt input pin -LIRQ5 through signal line [-INTP<5>].
!
CAUTION: Due to the PT-VME161 hardware implementation the "vectored" option must
always be used for the SCV64 Local Interrupts 5 and 4 Control Register 5AV bit.

VMEbus Interrupts

The VMEbus interrupts map directly onto the 68060 CPU interrupt levels. Each has its own
enable bit and each is always vectored. All VMEbus interrupts are level sensitive and not
latched, nor can their status be directly determined, with the exception or IRQ1*. See the
SCV64 User's Manual for more information on this exception.
The SCV64 VMEbus Interrupt Enable Register allows the individual interrupt request levels to
be enabled or disabled.

Interrupt Acknowledgment

The SCV64 interrupt handler generates the acknowledgment signals during the 68060 IACK
cycle to: auto-vector the cycle, indicate to Local Interrupt level 5 and 4 requesters that they must
supply a vector, or requests the SCV64 to obtain the VMEbus for a VMEbus interrupt acknowl-
edge cycle.
The order of priorities within any given interrupt request level is auto-vector first, followed by
Local Interrupt level 5 and 4 and finally VMEbus.

VMEbus Requester

Several request and release modes can be selected via the SCV64 Requester Control Register.
The bus release options include: Bus Clear [BCLR*], VMEbus ownership timer, and Release
on Request (ROR) or Release when Done (RWD).
Extensible Single Board Computer/Controller User's Manual 43
Performance Computer