Vmebus Slave Accesses; Scv64 Register Access From The Vmebus; Epak Access From The Vmebus; Vmebus Master Accesses - Performance Computer PT-VME161 User Manual

VMEbus Slave Accesses

The Slave Image is the VMEbus address range throughout which the local memory of the board can
be accessed. The slave image of the PT-VME161 is defined in programmable registers of the
SCV64. Separate slave images, different in size, can be set up in the A64, A32 and A24 address
spaces. The SCV64 does not provide an A16 slave image. The respective slave images are defined
by base address and size registers. The A64 image base address can be programmed to start on any
4 gigabyte boundary and is size 128 megabytes in size. A64 addressing is only supported during D64
Multiplexed Block Transfers (D64MBLT). The A32 image base address can be programmed to start
on any 128 megabyte boundary and be any size from 4 kilobytes to 128 megabytes in binary incre-
ments. The A24 image base address can start on any 512 kilobyte boundary or multiple of its
programmed size, whichever is larger, within the 16 megabyte A24 addressing space. The A24
image size can be programmed to 512K, 1, 2, or 4 megabytes.
The SCV64 responds to Standard and Extended, non-privileged and supervisory address modifiers.
VMEbus Access types include read, write and read-modify-write. Up to 128 megabytes of each
slave image can be protected from writes, or reads and writes.
Parity is generated and checked by PT-VME161 hardware on local DRAM Accesses by VMEbus
masters. A level 7 interrrupt may be generated if a parity error is detected. See "Parity" on page 30
for more information.

SCV64 register access from the VMEbus

The SCV64 provides a means for accessing its internal registers from the VMEbus. Since the DARF/
ACC did not support this feature, this capability is disabled on the VME161. Any attempts to access
SCV64 registers from the VMEbus will be treated as slave memory accesses and will access local
VME161 DRAM. Note that this effectively disallows the use of the (new) SCV64 Mailbox registers.
The SCV64 AUTOBAR feature (powerup assignment of slave address) is not used.

EPAK access from the VMEbus

See "EPAK Interface" on page 57.

VMEbus Master Accesses

The SCV64 can request the VMEbus under a number of conditions: the transmit FIFO contains write
cycles, the DMAC starting transfers, the 68060 begins a read cycle to the VMEbus, the SCV64 is in
atomic mode and the 68060 begins a write cycle to the VMEbus, or the SCV64 was signaled with a
VMEbus [IACK*] to begin an interrupt acknowledge cycle.
The SCV64 provides an Ownership Timer which can be programmed to limit the time that the
SCV64 maintains VMEbus mastership, from immediately off to 2, 4, or 8 ms., to unlimited use. The
Ownership Timer is used to ensure predictable bus access latencies to other VMEbus masters.
While performing bus transactions from the FIFO the VMEbus "address pipelining" feature is used.

68060 Accesses

CPU Accesses can be set up to be decoupled or atomic. In decoupled mode the FIFO accepts
the data, acknowledges 68060 writes then, the VMEbus immediately requests the bus. In atomic
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Performance Computer