Performance Computer PT-VME161 User Manual page 117

Performance Computer
SCV64, the same memory locations are selected. Otherwise, it is possible that different areas of local
memory could be accessed through those three paths.
The restriction on the slave image base is that it must be a multiple of the amount of memory
installed on the CPU card. For example, if the card had 4Mb of memory, the possible A24 slave
image bases would be 000000h, 400000h, 800000h, and C00000h, irrespective of the A24 size
programmed. It's not expected that this slave base restriction will be a problem for A32 images, since
they are already multiples of 128Mb.
Part or all of the slave image can be protected from either writes, or reads and writes. If an access is
made to the protected area from the VMEbus slave image, the SCV64 will respond with a bus error.
Protection is not implemented for memory accesses by the local CPU to its own slave images. The
PROT bit in the SCV64 Mode Control Register is used to select read/write protection options.
The lower four bits of the SCV64 Access Protect Boundary Register select how much of the lower
part of the slave images (this affects both the A24 and A32 image in the same way) is protected; 0
selects none protected, 1 selects the lower 64Kb, through to F protecting the lower 128Mb.
!
CAUTION: It is possible to protect the entire slave image, in which case the location monitor would
also be protected (from the VMEbus only, not from a local access using the slave image).
To change the receive mode between atomic and decoupled, incoming slave cycles must be disabled
first by writing zero to the VINEN bit in the SCV64 Mode Control Register, then waiting until the
SCV64 acknowledges the new mode by setting VINEN to zero. The SCV64 Mode Control Register,
RXATOM bit may then be changed and VINEN set high again. Any slave VMEbus accesses to the
SCV64 during this time will be ignored, which may cause a time-out bus error to be received by the
master performing the cycle.
Read accesses to the SCV64 are always atomic; if the SCV64 is in decoupled mode, a read access
by the slave will wait until any writes queued up in the FIFO are completed. Due to the wait while
up to seven writes must be done before the read, it is recommended that the VMEbus data transfer
time-out be longer than 4 microseconds.
If the SCV64 receives a local bus error while performing an queued write from a slave card, the
LBERR bit will become set in SCV64 Control and Status Register, and an interrupt will be gener-
ated. The SCV64 will not stop transferring cycles in or out, and does not save the faulted cycle for
diagnostics.
The SCV64 will request the local bus whenever it has cycles waiting in the receive FIFO, an atomic
VME-in cycle is pending, or the DMA needs to read/write local memory. The SCV64 can be
requested to give up the local bus if a higher priority device needs it.
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