System Control Register 2 - Performance Computer PT-VME161 User Manual

System Control Register 2

Bit
0
1
2
4-3
5
6
7
1
DRAM MUST be initialized before parity checking is enabled.
2
DO NOT enable if EBP = 1.
3
DO NOT enable if EPEC = 1.
4
RITI always read as 0.
5
SCV64 DMA burst cycle length must be set to 4.
Address 50000000h
Byte Read/Write Only
All bits cleared to zero by reset, except ETTI
7 6 5 4 3
Name Function
EEAV Enable EPAK Access from VMEbus
1 Enable EPAK Access from VMEbus when A24 = 1
0 Disable EPAK Access from VMEbus
1,2
EPEC Enable Parity Error Checking
1 Check for parity errors
0 Do not check for parity errors
3
EBP Enable Bad Parity
1 Write bad parity
0 Write normal parity
4
RITI Reset Interval Timer Interrupt pending latch
3 Reset Interval Timer 2 Interrupt Pending Latch
2 Reset Interval Timer 1 Interrupt Pending Latch
1 Reset Interval Timer 0 Interrupt Pending Latch
0 No action
EITI Enable Interval Timer Interrupts
1 Enable interrupts
0 Disable interrupts
ETTI Enable Tick Timer Interrupts
1 Enable interrupts
0 Disable interrupts
5
ESNP Enable Bus Snooping
1 Enable Snooping
0 Disable snooping
Extensible Single Board Computer/Controller User's Manual 63
2 1 0
EEAV
EPEC
EBP
RITI
EITI
ETTI
ESNP
Performance Computer