Initialization; Testing; Prom/Sram Sockets; Nonvolatile Sram And Time Of Day/Calendar Clock - Performance Computer PT-VME161 User Manual

Initialization

DRAM must be initialized before enabling parity error checking. The initialization process consists
of writing any data value to all installed memory locations. This operation sets the parity RAM to a
valid state.

Testing

For testing purposes bad parity may be intentionally written. By setting the Enable Bad Parity bit (2)
in Control Register 2, the parity bit written with each data byte will be complemented causing a
parity error to be generated when the byte is read.
NOTE: If EBP is enabled then the Enable Parity Error Checking (EPEC) must be disabled, other-
wise parity errors will be generated on every memory reference.
Diagnostics should include checking parity on an individual byte basis to fully check the parity
RAM.

PROM/SRAM Sockets

The board is equipped with two 32-pin JEDEC sockets configured as bytewide ports. Both sockets
support ROM, PROM, EPROM and Flash EPROM read-only devices, as well as 28-pin or 32-pin config-
urations.
One of the two sockets is also capable of supporting SRAM and Nonvolatile SRAM read/write devices.
Jumpers are provided to select between read-only and read/write operation and the 28-pin or 32-pin
configurations. See " U24 PROM/ROM/SRAM/EEPROM Socket Configuration" on page 14.

Nonvolatile SRAM and Time of Day/Calendar Clock

The Dallas Semiconductor DS1643 Nonvolatile Timekeeping RAM features 8184 Bytes of Nonvolatile
SRAM and a Real Time Clock (RTC) with integrated crystal, power fail control circuit and a lithium
energy source. The clock registers are Accessed identical to the static RAM. The registers reside in the
top eight RAM locations. The the base address of the Timekeeping RAM is at 0F000000h. See "Table
7: DS1643 Nonvolatile Timekeeping RAM Registers" on page 71 for more information.

Serial EEPROM

The EEPROM supports 128 bytes of nonvolatile memory. The part is capable of 10,000 erase/write
cycles and ten year data retention. Performance Technologies normally uses this memory to store various
parameters and options used in the initialization and operation of the PT-VME161.
This device is socketed so that it can be moved to another board if necessary. For instance, if board level
replacement is typically performed on failures in the field, the EEPROM can be moved to the replace-
ment board to maintain the configuration information of the original board.
Extensible Single Board Computer/Controller User's Manual 31
Performance Computer