Reset; Local Bus Timer; Watchdog Timer; Tick Timer - Performance Computer PT-VME161 User Manual

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Section FUNCTIONAL DESCRIPTION
but the SCV64 loads the cycle into its receive FIFO from its own I/O pads. The loopback acquires
mastership of the VMEbus for the process but the data read back through the Receive FIFO Address,
Data, and Receive Registers does not pass through the VMEbus buffers.
If a Bus Error [BERR*] occurs during a write to the VMEbus the VBERR bit in the Control and
Status Register is set, asserting the VMEINT pin. The Transmit FIFO Data, Address, and Control
Registers will contain the respective information for the bus cycle in error. When the VBERR bit is
cleared the SCV64 resumes with the next cycle in the FIFO.
If a Local Bus Error [-KBER] occurs during a write from the VMEbus the LBERR bit in the Control
and Status Register is set, asserting the VMEINT pin. The Receive FIFO Data, Address, and Control
Registers will contain the respective information for the bus cycle in error. When the VBERR bit is
cleared the SCV64 resumes with the next cycle in the FIFO.

Reset

The Reset block provides control of the PT-VME161 local reset signal [-LRST]. Local Reset is
asserted when the PT-VME161 detects a power on condition, if VMEbus [SYSRST*] is asserted,
the front panel Reset button is pressed, the watchdog timer expires, or software sets the SWRST bit
in the SCV64 General Control Register.
Local Reset will also be asserted if the SCV64 is the VMEbus System Controller and VMEbus
[BG0IN*] is asserted.

Local Bus Timer

The Local Bus Timer is used to recover from unsuccessful local transfers (internal to the
PT-VME161). If a Local Dtack [-KSA0] is not detected within 512 us. of the assertion of Local Data
Strobe [- KDS] the SCV64 will assert Local Bus Error [-KBER] until the Local Data Strobe signal
is released. The timer duration is not user programmable, however it can be disabled by the control
bit LTOEN in the SCV64 General Control Register.
References to UNASSIGNED addresses on the Local Bus will not generate Local Dtack, requiring
the time-out mechanism for recovery. If the timer is disabled and such a condition occurs, the CPU
will hang. It is recommended that the timer only be disabled in a system development environment.
The timer is automatically enabled after the assertion of reset.

Watchdog Timer

The Watchdog Timer can be used to recover from software failures. The timer's 2 seconds delay is
restarted automatically by the release of Power On Reset [-PRST] and under program control by 0
to 1 transition of the CLRDOG bit in SCV64 Status Register 0. Failure to toggle the CLRDOG bit
before the 2 seconds delay expires results in the assertion of Local Reset [-LRST]. Local Reset
initializes the 68060 and all I/O devices on the PT-VME161.
The Watchdog Timer can be enabled/disabled by the enable bit in the MISCO register.

Tick Timer

The Tick Timer is a user programmable timer in the SCV64. It can be set to one of two different
modes by the TICKM bit in the SCV64 Control and Status Register: normal or fast. In normal mode,
the interval can be set to 5, 10, 50, or 100 ms. In fast mode, the interval can be set to 0.2, 0.4, 2.0, or
4.0 ms. The intervals are selected by the TLEN1 and TLEN0 bits in the SCV64 General Control
38 Extensible Single Board Computer/Controller User's Manual