68040 Cache Control Registers - Performance Computer PT-VME161 User Manual

many read cycles can be performed internal to the chip while the longer external write cycles are
executing. Address spaces where writes and reads may be out of sequence with respect to each other
are said to be nonserialized. Note that reads are performed in the order found in the code and writes
are also performed in order. It is the order of writes with respect to reads that may be out of sequence.
Also, the 68040 will not do a read from an address that is still in the write queue.
Problems may arise with I/O devices where a read from a data register may depend on a write to a
different register. In these cases, because the addresses are different, the 68040 has no way of deter-
mining the dependency of the read and write instructions so that the register read may occur before
the write.
One way to remedy this situation is to place a NOP instruction before an I/O device register read.
The NOP has the effect of freezing instruction execution until all pending bus cycles complete. The
NOP, in effect, forces serialization.
A more general way to force serialization of I/O accesses is to use the 68040's Transparent Trans-
lation Registers. These registers operate independently of the 68040's MMU and are also available
on the 68EC040 and the 68LC040. There are two registers for data accesses (DTTR0 and DTTR1)
and two for instruction accesses (ITTR0 and ITTR1). The registers are read and written using the
MOVEC instruction in Supervisor mode.
!
CAUTION: The Transparent Translation Registers allow instruction and data address spaces to have
their serialization and cacheability controlled using address mapping. In the case of the PT-
VME151A, 8-bit devices and the EPAK need to be serialized and specified as noncacheable for data
accesses.
To accomplish this the following values must be written to the DTTRs (using the MOVEC instruc-
tion) at initialization.
DTTR0 - 000FE040h
maps addresses 0xxxxxxxh as serialized, noncacheable.
These addresses include: EPROM socket, EPROM/SRAM socket, 68681 DUART, Control/
Status Registers, SCSI MAR, Real Time Clock, and FAS216 SCSI chip.
DTTR1 - $102FE040
maps addresses 1xxxxxxxh and 3xxxxxxxh as serialized, noncacheable.
These addresses include: DARF internal registers, ACC and EPAK.
Since instruction space implicitly uses reads only, serialization is not an issue and the Instruction
Translation Registers are not enabled. The user is free to use the Instruction Translation Registers as
he sees fit.
If the MMU of the 68040 is used, each page descriptor may also control serialization and cache-
ability.

68040 Cache Control Registers

NOTE: The user should note that the 68040 cache control register format is different from the format
of the 68030.
Extensible Single Board Computer/Controller User's Manual 95
Performance Computer