Microprocessor; Memory; Dram - Performance Computer PT-VME161 User Manual

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Section FUNCTIONAL DESCRIPTION
Through the remainder of this document references to the Motorola MC68060 processor imply the
MC68EC060 also. Specific differences will be cited as necessary.

Microprocessor

The PT-VME161 utilizes a Motorola MC68060 microprocessor running at 50 MHz. This processor
combines a full 32-bit Central Processing Unit (CPU) core, a data cache, an instruction cache, a Floating
Point Processor, and an enhanced bus controller in a single VLSI device. The MC68EC060 is identical
to the MC68060 except that it lacks the MMU and FPU. The MMU of the 68060 may be disabled by
installing jumper K2.

Memory

There are four separate memory mechanisms available on the PT-VME161: up to 64 megabytes of
DRAM, two 32-pin JEDEC sockets for ROM, PROM, EPROM, etc., 8184 bytes of nonvolatile SRAM,
and 128 bytes of nonvolatile EEPROM.

DRAM

The main memory is composed of 70 ns. fast page mode DRAM. Available memory configurations are
4, 8, 16, 32, or 64 megabytes of DRAM. All of main memory can be mapped to the VMEbus through the
SCV64. Additionally, EPAK address space may be mapped to the VMEbus by overlaying its address
space with a portion of main memory. The overlaying is enabled at reset, making a portion of the main
memory inaccessible for the VMEbus. If the ability to address the EPAK from the VMEbus is not
desired, it may be removed by writing a 1 to the Enable EPAK Access from VME bit (0) of Control
Register 2. See "Enable EPAK Access from the VMEbus" on page 46 for more information.
The 68060 and 68EC060 support a burst mode for filling their on-chip data and instruction caches. The
PT-VME161 utilizes the fast page mode of the DRAM to accelerate the burst transfer operation. During
a burst transfer four sequential long words are fetched from the DRAM, requiring four clock cycles for
the first long word transfer and two clock cycles for subsequent long word fetches.
Parity
A Bus Error may be generated as an acknowledgement to a reference if a parity error is detected. See
"Parity" on page 30 for more information.
The address space from 20000000h to 2FFFFFFFh is allocated to the DRAM. Any reference to this 256
MByte space will complete without a bus error. The installed DRAM will repeat throughout this range.
Repeatability is described below. 'Blank' areas of memory cannot be written and will return unpredict-
able results when read. The DRAM size may be determined by reading the Status Register.
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Not availiable on 4M and 8M Configurations.
28 Extensible Single Board Computer/Controller User's Manual
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is generated and checked by PT-VME161 hardware on local DRAM Accesses by the MC68060.