68040 Cache Clearing; 68040 Exception Processing; Pt-Vme151A Control Register Differences; Table 24: Epak Caching - Performance Computer PT-VME161 User Manual

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Section APPENDICES

68040 Cache Clearing

NOTE: The user should note that the 68040 caches are disabled after a reset but are not cleared or
invalidated. The user needs to explicitly clear the instruction and data caches using the CINV
instruction as part of initialization.

68040 Exception Processing

NOTE: The user should note that 68040 exception processing differs from that of the 68030. In
particular, the format and lengths of some of the exception stack frames are different. The 68040
User's Manual should be consulted for further information.

PT-VME151A Control Register Differences

Since the cacheability of the 68040 address space is controlled using the Transparent Translation Regis-
ters, two bits in the System Control Register ECE and VCE, now have different meanings. Bit 6 (ECE)
is defined as EPAK Caching Enable and Bit 7 (VCE) is defined as VMEbus Caching Enable.
As described previously, cacheability of an address may be determined in hardware (using the TCI
signal), but the processor will still attempt to fetch four longwords to fill the cache line, but then discard
them. Cacheability may also be controlled using the 68040 Transparent Translation Registers to elimi-
nate the extra longword fetches and to control serialization.
EPAK address space is defined as noncacheable in the Transparent Translation Registers as defined
previously. Thus, the Enable EPAK Caching bit of the Control Register does not entirely control EPAK
cacheability (as it did in the VME131/141).
If an EPAK were to be constructed which could make use of data caching (such as an all-memory
EPAK), then the Transparent Translation would be redefined to allow EPAK caching. In this case, the
caching of the EPAK would then also depend on the state of the Enable EPAK Caching bit of the Control
Register.
In summary, in normal PT-VME151A operation with existing EPAKs, EPAK address space is defined
internal to the 68040 as non-cacheable. This makes the Enable EPAK Caching bit of the Control Register
irrelevant. Below are the possible combinations of events:
EPAK Cache Enable
With respect to VME memory space, VME space is not explicitly affected by the mapping defined above
in the Transparent Translation Registers. Therefore, the VME Caching Enable bit in the System Control
Register still controls the cacheability of VME address space. However, if the 68040 data caches are
enabled, but the VME Caching Enable bit in the System Control Register is false, VME address space
will not be cached, but the processor will still fetch four longwords from the VMEbus, afterwards
96 Extensible Single Board Computer/Controller User's Manual

Table 24: EPAK Caching

68040 DTTR 161 Control Register EPAK
Disabled
Enabled
Enabled
Cache Enable
Don't Care
True
False
EPAK Caching?
No (Normal mode)
Yes
No, but 4 lwords fetched