68060 Versus 68040 - Performance Computer PT-VME161 User Manual

Mode Register Initialization - Initialization code must set the BUSSIZ and SWAP bits of the SCV64
Mode Register (address $1800003C) to 1. These bits are set by PTBUG upon reset; initialization code
written by the user must set these bits. These bits were set automatically in the VME151/151A.

68060 Versus 68040

Code compatibility - according to Motorola, the 68060 is 100% user code compatible with the 68040
when used with the 68060 software package. The software package is provided free by Motorola and
implements the few integer and floating point instructions not implemented by the 68060. See the
"M68060 Microprocessor User's Manual" for more information.
Interrupts - interrupt service routines must start on longword boundaries.
Transparent Translation Registers - the 68060 transparent translations registers behave somewhat
differently on the 68060 than on the 68040. Additionally, there is a Translation Control Register which
must be initialized. The following values are written by PTBUG at initialization. Any user initialization
must set these values.
DTT0 = $200FC000 (caches DRAM accesses)
TC = $00000200 (default cache modes)
DTT1, ITT0 and ITT1 are not used.
Other 68060 features - the 68060 has architectural enhancements that give it a substantial increase in
processing power compared to the 68040. For example, a full 16 Mbyte DRAM test using a 68060
showed better than a 3 to 1 improvement over a 68040 using the same DRAM architecture. To fully
utilize the added features of the 68060, the ESS bit in the PCR (Enable Superscalar dispatch) should be
set. Likewise, the Branch Cache enable bit, EBC, and Store Buffer Enable bit, ESB, in the Cache Control
Register should be set. See the M68060 User's Manual for more information.
Extensible Single Board Computer/Controller User's Manual 91
Performance Computer