Location Monitor; Registers; Test And Diagnostics - Performance Computer PT-VME161 User Manual

The transfer rate over the VMEbus is a function of the master/slave handshaking rate and transfer
mode. When "decoupled" D64MBLT transfers were tested with the PT-VME240 VME64 Memory
Board a burst transfer rate exceeding 53 megabytes per second was measured.
DMA completions and errors can generate interrupts to the 68060, through interrupt handler of the
SCV64 ([- INTP<1>], LIRQ1).
The advanced features of the SCV64 can be used to tune DMAC and VMEbus performance. The
Transmit FIFO can be configured to begin VMEbus transfers immediately upon having data, or
configured to wait until the FIFO is full. The No-Release mode (NOREL) bit in the SCV64 Mode
Control Register causes the SCV64 to maintain ownership of the VMEbus until either the SCV64
requests the SCV64 to release the bus, or until the bit is turned off. The Ownership Timer in the
SCV64 can be used in conjunction with the NOREL bit to throttle DMAC use of the VMEbus. By
using the DMA Burst Enable and FIFO Burst Enable bits the "Burst Mode" feature of the respective
mechanism can be enabled. The length of burst transfers on the local bus can be throttled with the
BLEN field of the SCV64 Mode Control Register. When bus snooping is enables (bit 7, system
CTRL Reg2), the burst lenght must be set to 4 (BLEN = 00) for proper snoop operation.
Parity is generated and checked by PT-VME161 hardware on local DRAM Accesses during DMAC
operation. A level 7 interrrupt may be generated if a parity error is detected. See "Parity" on page 30
for more information.

Location Monitor

The location monitor assists in inter-processor and inter-process communication. It consists of a 32-
bit wide, 31-entry deep message FIFO loaded from the VMEbus. D32 or D16 operations are
supported. If the even word is written, the upper 16 bits of the FIFO entry are set to one. The message
FIFO is not bidirectional.
The Location Monitor exists at the top longword and the lower (even) word of the top longword in
each of the A32 and A24 slave images. The monitor is equally accessible by the VMEbus and the
local CPU. A process on the PT-VME161 does not need to determine whether the process it's
sending a message to is local or not.
The existence of entries in the message FIFO can generate interrupts to the 68060, through interrupt
handler of the SCV64 ([- INTP<0>], LIRQ0).

Registers

The SCV64 is a longword wide device with 16 directly addressable internal registers. Status bits are
generally sampled by the SCV64 at the start of a register access cycle to ensure up-to-date data for
the reference. Detailed descriptions of the registers are available in the SCV64 Technical Manual, a
summary is provided in "Table 6: SCV64 Register Map" on page 69. Bits that are unused have
defined values and may be used in future versions of the SCV64. It is recommended that such unused
bits be masked to zero before writing or after being read by software to maximize the probability of
future software compatibility.

Test and Diagnostics

The Loopback Enable bit (LPBK) in the SCV64 Mode Control Register allows the CPU to test the
address and data paths and the control logic. In Loopback mode any write cycle to its own slave
image by the CPU does not go directly to memory, but goes out on the VMEbus then back in again
through the FIFOs. The VMEbus address and data transceivers drive the cycle onto the VMEbus,
Extensible Single Board Computer/Controller User's Manual 37
Performance Computer