Enable Interval Timer Interrupts; Enable Tick Timer Interrupts; Enable Bus Snooping - Performance Computer PT-VME161 User Manual

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Section FUNCTIONAL DESCRIPTION
Reset Interval Timer Interrupts

Enable Interval Timer Interrupts

Enable Tick Timer Interrupts

Enable Bus Snooping

48 Extensible Single Board Computer/Controller User's Manual
The RITI bits are encoded to reset the Request Latch of the individual Interval Timers. When
an Interval Timer reaches it's terminal count, the event is recorded by its Request Latch. The
outputs of the three Request Latches are OR'ed together, generating the Interval Timer Interrupt
Request to the 68060. The interrupt request from an individual Interval Timer remains active
until its Request Latch is reset using this field.
Value Function
3 Reset Interval Timer 2 Request Latch
2 Reset Interval Timer 1 Request Latch
1 Reset Interval Timer 0 Request Latch
0 No action
RITI is a two bit field. It consists of register bits 3 and 4, where bit 3 is the least significant bit.
This field is always read as 0.
All interrupt requests from the three Interval Timers can disabled. When the EITI bit in System
Control Register 2 is cleared (0) Interval Timer interrupt requests are disabled. When set (1)
they are enabled. Local Reset clears (0) this bit, disabling Interval Timer interrupts. EITI is
register bit 5.
Interrupt requests from the SCV64 Tick Timer can disabled. When the ETTI bit in System
Control Register 2 is cleared (0) Tick Timer interrupt requests are disabled. When set (1) they
are enabled. Local Reset sets (1) this bit, enabling Tick Timer interrupts. ETTI is register bit 6.
Bus snooping allows invalidation of 68060 cache entries when DRAM is written by a bus
master other than the 68060. Without snooping, DMA operations can update DRAM while the
68060 retains old data in its internal caches.
Note: When bus snooping is enabled, the SCV64 DMA burst cycle length must be set ot 4 for
proper operation.
Snooping is disabled after a reset.