Read-Modify-Write; Dmac - Performance Computer PT-VME161 User Manual

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Section FUNCTIONAL DESCRIPTION
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Read-Modify-Write

DMAC

The DMA Controller in the SCV64 can transfer data between the VMEbus and DRAM or EPAK
memory in several different address and data modes. It is controlled through four internal registers:
DMA Local Address Register, DMA VMEbus Address Register, DMA Transfer Count Register,
and the SCV64 Mode Control Register.
The DMAC can be programmed to use A64, A32, or A24 addressing, in supervisor or nonprivilege
mode. The upper 32 bits of the A64 address are static and provided by the Master A64 Address
Register. The lower 32 bits of the A64 address and A32 or A24 addresses are provided by the DMA
VMEbus Address Register.
Data transfers can be programmed to occur in discreet (D32/D16), block (D32BLT/D16BLT), or
multiplexed block (D64MBLT) mode. The DMA Transfer Count Register allows up to 4 megabytes
of data to be transferred. The hardware automatically releases Address Strobe on the proper bound-
aries on the local and VMEbus.
To further improve transfer rates the PT-VME161 supports "Burst Mode" transfers from the SCV64
on the local bus. Burst lengths of 4, 8, 16, or 32 longwords can be programmed using the BLEN field
of the SCV64 Mode Control Register. Given 32 longword bursts and the 4-2-2-2...2 DRAM burst
timing a maximum data transfer rate of 49.2 megabytes per second is achievable over the local bus.
The DMA Burst Enable (DMABEN) and FIFO Burst Enable (FIFOBEN) bits in the SCV64 Mode
Control Register allow the "Burst Mode" feature of the individual mechanisms to be enabled.
36 Extensible Single Board Computer/Controller User's Manual
mode the FIFO is bypassed and the CPU waits for the VMEbus acquisition and transfer to take
place. All 68060 reads bypass the FIFO.
Access to the VMEbus address space by the 68060 CPU is through addresses 80000000h -
FFFFFFFFh. In order to access the full VMEbus address space the Page bit in the 161 System
Control Register defines VMEbus address bit 31. When the Page bit is 0, PT-VME161
addresses 80000000h-FFFFFFFFh are mapped to VMEbus addresses 00000000h -
7FFFFFFFh. When the Page bit is 1, PT-VME161 addresses 80000000h-FFFFFFFFh are
mapped to VMEbus addresses 80000000h-FFFFFFFFh.
For CPU Accesses the SCV64 splits 4 Gigabyte VMEbus address space into 32-128 megabyte
pages. Most pages are defined to be A32:D32, however selected ranges may define to be
A24:D32, A24:D16 and A16:D16 spaces.
CAUTION: When the CPU performs an Access in the A16:D16 range, the SCV64 will respond
to the CPU as a 16 bit device, unlike the 68030, the 68060 will NOT split up the cycles if neces-
sary. Similarly, for references in the A24:D16 space.
A24:D32 and all A32 Accesses allow 32 bit transfers from the 68060. The implied addressing
space and the CPU function codes determine the data or program, and supervisory or nonpriv-
ileged aspects of the Address Modifier code.
The SCV64 is capable of supporting single address Read-Modify-Write MC68060 instructions
(TAS) across the VMEbus. The 68060 CAS and CAS2 instructions can require two addresses
during a "locked" operation, thus translating into a requirement for Address Strobe to be
asserted twice on the VMEbus while remaining "locked" in between. The VMEbus Specifica-
tion provides no mechanism for supporting this class of operations.