Location Monitor; Vmebus Master Memory Map - Performance Computer PT-VME161 User Manual

Location Monitor

The location monitor is a specialized function of the SCV64 to assist in inter-processor communica-
tion. It is a 32-bit wide, 31-entry deep message FIFO loaded from the data bus when the location
monitor is written to, so that either 16- or 32-bit messages or memory pointers can be sent between
processes. This FIFO is written to using the slave image VMEbus address and is read by the local
CPU. Writing to this location is the method defined for exiting from BI-mode, enabling the card to
perform master and slave VMEbus accesses.
The location monitor's address exists at the top longword and the lower (even) word of the top long-
word in each of the A24 and A32 slave images presented on the VMEbus. It replaces the longword
of memory (that is accessible through the slave images) which would otherwise exist at that address,
so writes to the location monitor do not enter into memory (however, that memory location is still
accessible by the local bus). In order for the local CPU to access its own location monitor, it must
also use the A24 or A32 slave image VMEbus address. When the CPU writes to this specialized
location (or accesses any other location in the slave image), the transfer does not involve use of either
the transmit FIFO or the VMEbus.
If the location monitor FIFO is full when a write to it is made, the cycle will not be responded to. If
the local CPU reads out an item while a write is waiting on the other end, then a position would
become available and the write accepted. Otherwise, the bus time-out would expire and end the cycle
with a Bus Error.
Messages in the location monitor FIFO are read in the form of longwords from the Location Monitor
FIFO Read Port (LMFIFO). If a write happened to be 16 bits (the lower word of the top longword
of the slave image), then the upper 16 bits of that FIFO entry are recorded as ones. Once the FIFO
becomes empty, further reads will return undefined data.
A status bit (LMHD) is available in the Control and Status Register (DCSR) which is high when the
FIFO has data available for the local CPU to read. While there are entries in the FIFO, the SCV64
generates an interrupt request to the local CPU. This allows software to either poll the status bit or
the interrupt request signal, or use an interrupt service routine to support the location monitor.

VMEbus Master Memory Map

The programmable memory map of the SCV64 determines the type of cycle to perform on the
VMEbus during discrete master transfers (DMA excluded). When the CPU accesses the VMEbus,
the address used by the CPU determines the address and data modes the SCV64 will use to perform
the cycle. The valid bits (depending on the addressing mode) of this address will always map directly
to the VMEbus, while the unused bits are used by the SCV64 to determine the type of cycle. For
example, when the CPU attempts to access an A24 device on the VMEbus, the top 8 bits of the 32-
bit address sent to the SCV64 are used to signal that an A24 address modifier is needed. The possible
addressing modes are A16, A24, or A32, and the data modes are D16 or D32. (Note: additional
addressing and data modes, i.e. A64, D64MBLT, etc., are available in DMA mode). All addresses
that are not defined as A16 or A24 space cause the SCV64 to use A32:D32 mode when using the
VMEbus. The "SCV64 Memory Map" on page 100 provides a graphical representation of how these
different modes are organized in the memory map.
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