Interval Timer; Figure 11: Interval Timer Block Diagram - Performance Computer PT-VME161 User Manual

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Section FUNCTIONAL DESCRIPTION

Interval Timer

The Interval Timer, an Intel 82C54, provides three independent 16-bit timers running off the same 4 MHz
clock. These three timers are identical in operation. Refer to the Intel Peripherals Handbook for a
complete description of the 82C54
When an Interval Timer is programmed in "Mode 2", it will perform the following functions when it
counts down to zero: pulse its OUTPUT pin, reload the initial count, and continue counting. The output
pulse of each timer is latched into the respective Interval Timer Interrupt Request Latch and the outputs
of the three latches are OR'ed together to generate the Interval Timer Interrupt Request.
Interval Timer
4 MHz
Interval Timer
Clock
Interval Timer
System Control
Register 2
RITI0-RITI1
EITI
The Interval Timer Interrupt Request generates an interrupt through the LIRQ2 pin of the SCV64. This
pin is shared with the SCV64 Tick Timer (which can be disabled). The Interval Timer Interrupt Request
can be enabled by setting the EITI bit (5) in System Control Register 2. When the Interval Timer inter-
rupts are disabled, the latching of the individual timer output pulses is also disabled. After reset, the state
of the 82C54 is undefined so the Interval Timer interrupts are disabled.
An interrupt on the LIRQ2 pin can be programmed (in the SCV64 Local Interrupts 3 and 2 Control
Register) to generate an auto-vector operation on any one of the 68060's seven interrupt request levels.
Any of the Interval Timers may have its counting disabled by programming it to "Mode 1". Mode 1
requires a rising edge on the timer's GATE input to enable counting. Since each GATE input is hard-
wired to logic 1, Mode 1 will never count and thus may be used as a "Disable Counting" mode.
The current state of the individual Interval Timer Request Latches (0, 1, and 2) may be determined by
reading the Interval Timer Interrupt Pending bits in System Status Register 3. SSR3 bits 4, 5, and 6 reflect
the state of ITIP0, ITIP1, and ITIP2, respectively.
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See "Applicable Documents" on page 2 for Intel Peripherals Handbook ordering information.
32 Extensible Single Board Computer/Controller User's Manual
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Figure 11: Interval Timer Block Diagram

Output
0
Interval Timer 0
Reset
Request Latch
1
Interval Timer 1
Request Latch
2
Interval Timer 2
Request Latch
decoder
Interval Timer
Interrupt Request
System Status
Register 3
ITIP0
ITIP1
ITIP2