System Status Registers; System Status Register 1; Hex Switch; System Status Register 2 - Performance Computer PT-VME161 User Manual

System Status Registers

The System Status register provides the PT-VME161 with status information not provided in other regis-
ters. It is a read only register. All unused bits (31-4) should be masked to zero (0) for future expansion.
This register should only be referenced using byte operations. Reading it as a word or longword will be
translated into multiple byte reads by the sizing logic, with the same data byte being repeated on each
reference.

System Status Register 1

System Status Register 1 is an 8-bit, read only register. This register resides at location 0C000000h.

Hex Switch

The current setting of the front panel hexadecimal switch can be read through this register. The
hex switch value will be presented as a nibble on data bits 3-0 at location 0C000000h (bit 0 is
the least significant bit). This four bit field is referred to as HSW.

System Status Register 2

System Status Register 2 is an 8-bit, read only register. This register resides at location 60000000h.

68060 Parity Error

When the 68060 Parity Error bit (named 060PE) is read as 1, it indicates that a parity error was
detected during a 68060 DRAM read cycle. Notification of the error is through a Bus Error that
is generated as a acknowledgment on the DRAM reference. The Bus Error Handler must check
this bit to determine if bad DRAM parity was the source of the Bus Error. 060PE is cleared by
reset and after each time System Status Register 2 is read. 060PE is register bit 1.

SCSI DMA Parity Error

When the SCSI DMA Parity Error bit (named SDMAPE) is read as 1, it indicates that a parity
error was detected during a SCSI DMA DRAM read cycle. Notification of the error is though a
level 7 Interrupt to the 68060 that is generated immediately after the DRAM reference in error.
The Level 7 Interrupt Handler must check this bit to determine if bad DRAM parity was the
source of the interrupt. SDMAPE is cleared by reset and after each time System Status Register
2 is read. SDMAPE is register bit 2.
SCV64 Parity Error
When the SCV64 Parity Error bit (named SCV64PE) is read as 1, it indicates that a parity error
was detected during a SCV64 DRAM read cycle. Notification of the error is though a level 7
Interrupt to the 68060 that is generated immediately after the SCV64 reference in error. The
Level 7 Interrupt Handler must check this bit to determine if bad SCV64 parity was the source
of the interrupt. SCV64PE is cleared by reset and after each time System Status Register 2 is
read. SCV64PE is register bit 3.
Extensible Single Board Computer/Controller User's Manual 49
Performance Computer