Pt-Vme151A Differences From Vme131/141; Darf64 Uses 68040 Mode; Scsi Controller Differences; Effects Of 68040 Vs. 68030 - Performance Computer PT-VME161 User Manual

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Section APPENDICES
APPENDIX H: PT-VME151A Differences From VME131/141
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NOTE: The following Appendix has been provided for customers that are upgrading from a PT-
VME131/141 to the PT-VME161. Information in this Appendix must be used to change native PT-
VME131/141 code to PT-VME151A code before applying changes needed for the PT-VME161.
This appendix is an overview of the programming issues that must be considered when porting code from
the PT-VME131/131E or PT-VME141/141E to the PT-VME151A.

DARF64 uses 68040 mode

The PT-VME151A is configured in hardware to automatically come up in 68040 mode. This means that
a read from the DARF64 Mode Control Register will show a 1 in bit 24 (040 mode enabled) instead of
0 (as in VME141).
One effect of 68040 mode is that longword writes by the 68040 to D16 VME space will fail.

SCSI Controller differences

Alternate DMA mode in Emulex SCSI chip is no longer used. This means that the Alternate DMA mode
bit of FAS216 Configuration Register 3 is written with 0 rather than 1 (as in VME131/141).

Effects of 68040 vs. 68030

Cacheability and Serialization

One difference between the 68040 and 68030 is the way cache line refills are handled. In 68030
cycles, devices may acknowledge themselves as noncacheable so that the 68030 will not attempt to
cache the data obtained during the read cycle. The 68040, however, will still fetch four longwords
to fill its cache line even if the device acknowledges itself as noncacheable (using the TCI signal).
In that case, the processor fetches the four longwords and then discards them internally, retaining the
original data sought.
What can happen, then, is that if an instruction reads a byte, the processor actually does four long-
word read cycles. These extra read cycles may potentially cause loss of data in I/O device registers
which are cleared after reading. They may also produce an error or unpredictable results when illegal
addresses are read.
When the caches are enabled, the entire address space is considered cacheable by default. It is neces-
sary to specify critical address spaces as noncacheable so that the processor does not attempt to do
cache refills, incurring the extra longword reads. The non-cacheability is specified using the 68040's
Transparent Translation Registers, discussed later.
To increase processing efficiency, the 68040 may not perform read and write bus cycles in the same
order found in the instruction stream. Write cycles may be queued internally while read cycles occur-
ring downstream in the code are executed. This can increase execution efficiency if the hit rate in
the data cache is high. Rather than forcing read cycles to wait for the completion of pending write
cycles (which usually require wait states), read data may often be found in the data cache. Thus,
94 Extensible Single Board Computer/Controller User's Manual