Scsi Dma Read/Write Direction; Epak Space Cache Enable; Vmebus Space Cache Enable; System Control Register 2 - Performance Computer PT-VME161 User Manual

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Section FUNCTIONAL DESCRIPTION

SCSI DMA Read/Write Direction

EPAK Space Cache Enable

VMEbus Space Cache Enable

System Control Register 2

System Control Register 2 is an 8-bit, read/write register. All bits except ETTI are cleared to zero
(0) by Local Reset. ETTI is set to 1 by Local Reset. This register resides at location 50000000h.
Enable EPAK Access from the VMEbus
46 Extensible Single Board Computer/Controller User's Manual
SDIR in the System Control Register determines the direction of a data transfer during a SCSI
DMA operation. Setting this bit will generate data movement from DRAM to the FAS216, a
write to the SCSI bus. Clearing it moves data from the FAS216 to DRAM, a read from the SCSI
bus. Local Reset clears (0) this bit (SCSI DMA Read).
The ability to cache information in the EPAK address space (30000000h-3FFFFFFFh) is deter-
mined by the MC68060 Transparent Translation Registers. This makes the Enable EPAK
Caching bit of the Control Register irrelevant. Below are the possible combinations of events:

Table 1: EPAK Caching Options

68060 DTTR
EPAK Cache Enable
Disabled
Enabled
Enabled
Local Reset clears (0) this bit, enabling caching. See "APPENDIX H: PT-VME151A Differ-
ences From VME131/141" on page 94 for an in-depth discussion of EPAK caching.
Reads from the VMEbus address (80000000h-FFFFFFFFh) space can be cached. When the
VCE bit in the System Control Register is cleared (0) VMEbus space caching is enabled. When
set (1) it is disabled. Local Reset clears (0) this bit, enabling caching.
The VCE bit is intended to enable or disable VMEbus caching. The Transparent Translation
Registers of the 68060 disable VMEbus caching by default, making the VCE bit of the System
Control Register One irrelevant. If the Transparent Translation Registers are used to enable
VMEbus caching, then the VCE bit must be set to 0 with a write operations to enable caching.
This feater provides backward compatability with the VME131/141/151/151A.
NOTE: If the VMEbus Page Select bit is toggled while caching is enabled a system failure could
result!
The EPAK expansion module can be Accessed by a VMEbus master as part of the PT-VME161
slave image when the EEAV bit is 0, the VMEbus address bit 24 is 1, and the A32SIZ field of
the DARF VMEBAR register is programmed to allow a A32 Slave Image Size greater than or
equal to 32MBytes (Dh). In this case a portion of the PT-VME161 slave image is replaced by
VME151 Control Register
EPAK Cache Enable
Don't Care
True
False
EPAK Caching?
No (Normal mode)
Yes
No, but 4 lwords fetched