Epak Interface - Performance Computer PT-VME161 User Manual

Performance Computer

EPAK Interface

The Performance Technologies family of Single Board Controllers features provisions for user defined
expansion modules. Two basic expansion module strategies are available. The "EPAK" is a 3" x 9"
mezzanine board which is intended for applications that must be limited to a single slot. The "EBOARD"
is a full-sized VMEbus 6U module which requires the use of a second slot. EBOARDs may be designed
with or without backplane Access.
The interface between the PT-VME161 and the expansion module is implemented using three 36-pin
connector strips (referred to in the Expansion Module Design Guide as J1, J2, and J3).
The interface is organized such that simple slave expansion modules need to connect only to the J1
connector, which provides 8 bits of address and data and the control signals to support this class of slave.
Adding a J2 connector to the expansion module brings the number of address lines up to 24 and the
number of data lines up to 16. Full A32:D32 slave, as well as all master expansion modules, must use all
three connectors.
Many signals on the expansion module interface are simply extensions of the MC68060 signal of a
similar name (MP prefix). Refer to the Motorola MC68060 User's Manual for additional information on
the behavior of these signals. Other signals are annotated as "Expansion" (EP prefix) and are uniquely
defined for this application.
The PT-VME161 partitions the expansion module (EPAK) memory space into two regions: the first
requires that the expansion module generate Data Size Acknowledgments (-EPSA0,1) to accommodate
the timing delay of the selected expansion module slave device, the second region requires no response
signal from the expansion module ([-EPSA0] and [-EPSA1] need not be driven). The second region
allows zero wait state Access to SRAM or registers on an EPAK.
The EPAK may be Accessed form the VMEbus as part of the PT-VME161 address space. To do so,
VMEbus address bit A24 must be 1, the EEAV bit in System Control Register 2 must be 0, and the
A32SIZ field of the DARF VMEBAR register must be programmed to allow an A32 Slave Image Size
greater than or equal to 32MBytes (Dh). See "Enable EPAK Access from the VMEbus" on page 46 for
more information.
Parity is generated and checked by PT-VME161 hardware on local DRAM Accesses by EPAK masters.
A Bus Error may be generated as an acknowledgement to a reference if a parity error is detected. See
"Parity" on page 30 for more information.
For more information refer to the Expansion Module Design Guide.
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