Atomic; Vmebus Control Logic - Performance Computer PT-VME161 User Manual

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Section FUNCTIONAL DESCRIPTION

Atomic

VMEbus Control Logic

The VMEbus interface of the SCV64 is fully asynchronous, thus avoiding the delays and reliability
problems associated with synchronous designs. The VMEbus data transfer control lines Address
Strobe [AS*], Data Strobe [DS0* and DS1*] and Data Transfer Acknowledge [DTACK*] perform
asynchronous handshaking to pass data across the bus. Any delays in turning these handshaking
signals around slow down the associated data transfer. In the SCV64 fully asynchronous design, the
delays are strictly a function of propagation times through the control logic.
Synchronous designs require sampling of the VMEbus transfer control signals in order to be reliably
used by the synchronous control logic. High sampling rates are necessary to achieve performance
equivalent to asynchronous designs, but these higher sampling rates increase the probability of meta-
stability conditions occurring. When a metastable condition does occur its statistical duration falls
off with time, therefore the longer that one waits to act upon the sampled signal the less likely they
are to see it metastable. A designer must make a performance vs. reliability trade off on what this
delay should be. This Metastability Settling Time will add a fixed delay to every sampled signal.
Another delay added by sampling is due to the sampling clock rate. An incoming signal can change
anywhere between two sample clock edges. Best case is when the incoming signal changes just
before the sample clock, worst case is when the incoming signal just misses the sample clock. On
the average, a Sampling Delay of one half of the sample clock time must be added to each sampled
signal.
Therefore, every signal that requires sampling must have a Sample Delay and Metastability Settling
Time must be added to propagation times of the control logic. All synchronous designs that interface
to the asynchronous VMEbus pay a performance penalty and make the associated performance vs.
reliability trade-offs.
34 Extensible Single Board Computer/Controller User's Manual
the VMEbus handshaking rate. The receive and transmit FIFOs can be individually enabled
using the RXATOM and TXATOM bits in the SCV64 Mode Control Register.
The receive FIFO captures write transfers from VMEbus devices or DMAC VMEbus reads.
Data can be moved into the FIFO using D64MBLT, D32BLT, D16BLT, or individual transfers.
As soon as there is data in the FIFO, the SCV64 requests the local bus and the data will be trans-
ferred to the appropriate address in DRAM or EPAK memory.
The transmit FIFO decouples local bus write references to the VMEbus, either from the CPU or
the DMAC. On DMA transfers you can optionally wait until the FIFO is full before writing to
the VMEbus. DMA data can be transferred from the FIFO using D64MBLT, D32BLT,
D16BLT, or individual transfers. CPU references are always handled as individual transfers. As
soon as there is data in the FIFO, the SCV64 requests the VMEbus and transfers the data to the
appropriate address.
If the FIFO Burst Enable (FIFOBEN) bit or DMA Burst Enable (DMABEN) bit in the SCV64
Mode Control Register is set then "burst mode" is used on the local bus to transfer the respective
data. Otherwise the incoming data will be moved as individual 32 bit references.
When the RXATOM or TXATOM bit in the SCV64 Mode Control Register is set, the respec-
tive FIFO is bypassed. In atomic mode, cycles are performed in direct-connected mode where
the address, data, DTACK and BERR signals are connected between the local bus and the
VMEbus.