Register Block; Interrupt Handler; Local Level 7 Sources; Abort - Performance Computer PT-VME161 User Manual

Register. The TICK pin of the SCV64 is asserted (driven low) each time the timer expires and
remains asserted until software resets it via the CLRTIK bit in SCV64 Status Register 0.
Assertions of the TICK pin are at multiples of the selected interval, not a new interval from the 0 to
1 transition of CLRTIK.
The TICK pin generates the Tick Timer Interrupt Request through the LIRQ2 pin of the SCV64. The
Tick Timer Interrupt Request can be disabled by setting the ETTI bit (6) in System Control Register
2. The current state of the TICK pin can be determined by reading the ITIP bits in System Status
Register 3 and the LI2 bit in the SCV64 Local Interrupt Status Register. If LI2 is asserted (1 =
asserted) and ITIP0, ITIP1, and ITIP2 are all negated (0) then a Tick Timer Interrupt Request is
pending. After reset, the Tick Timer Interrupt Request is enabled, maintaining compatibility with
PT-VME151.
An interrupt on the LIRQ2 pin can be programmed (in the SCV64 Local Interrupts 3 and 2 Control
Register) to generate an auto-vector operation on any one of the 68060's seven interrupt request
levels. See "Timer Event" on page 41.
This timer is not used by any PTI supplied software or firmware.

Interrupt Handler

The SCV64 Interrupt Handler prioritizes interrupts from dedicated local level 7 sources, general
purpose local sources and the VMEbus. The Interrupt Handler also allows each source to be individ-
ually enabled, each of the six general purpose sources to be mapped to any of the seven interrupt
levels and the status of any local interrupt to be read.
In the case of multiple active interrupts on a level that is being acknowledged, auto-vector sources
have the highest priority followed by local vectored interrupts and finally, VMEbus interrupts.
Details of PT-VME161 use of the SCV64 interrupt inputs follows:

Local Level 7 Sources

On the SCV64 there are five interrupts dedicated to level 7: the internal BI-mode signal and the
external L7INMI, L7IMEM, L7IACF and L7ISYF signals. On the schematics SCV64 symbol
the four external signals are labeled L7I0(NMI) [-INTP<6>], L7I1(MEM) [-INTP<7>],
L7I2(ACF) [-INTP<8>], and L7I3(SYF) [- INTP<9>], respectively. For detailed information
on the operation of the Level 7 interrupt mechanisms and the BI-mode signal refer to the SCV64
User's Manual.

Abort

Pressing the ABORT button on the front panel will generate a non-maskable interrupt to
the 68060. This interrupt request cannot be disabled. This input is edge sensitive and can
be reset by writing a zero to control bit NMIIE in SCV64 Level 7 Interrupt Status Register.
The current state of this signal can be read in the NMIIP status bit of the SCV64 Status
Register 0.
SCSI Bus Reset
When a RESET condition [RST] occurs on the SCSIbus a L7IMEM interrupt is generated
in the SCV64. The interrupt is enabled by setting the MEMIS bit in the SCV64 Level 7
Interrupt Status Register. The SCSI RESET condition is used to immediately clear all SCSI
Extensible Single Board Computer/Controller User's Manual 39
Performance Computer