1. Manuals
  2. Brands
  3. Performance Computer Manuals
  4. Controller
  5. PT-VME161
  6. User manual

Performance Computer PT-VME161 User Manual

Extensible single board computer/controller
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Performance
Computer
USER'S MANUAL
PT-VME161
Extensible Single Board Computer/Controller
A Performance Technologies Company
315 Science Parkway
Rochester, New York USA 14620
Document Number 126A0190

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PT-VME161 and is the answer not in the manual?

Questions and answers

Related Manuals for Performance Computer PT-VME161

Summary of Contents for Performance Computer PT-VME161

  • Page 1 Performance A Performance Technologies Company 315 Science Parkway Computer Rochester, New York USA 14620 USER’S MANUAL PT-VME161 Extensible Single Board Computer/Controller Document Number 126A0190...

  • Page 2: Copyright Notice

    Technical Publications at (716) 256- 0200 or pccsupport@pt.com. All comments, suggestions, and criticisms are welcome. Copyright Notice © 1993-1994 by Performance Computer, a Performance Technologies Company. -- Printed in USA. 315 Science Parkway, Rochester, New York 14620 Trademarks Microware and OS-9 are trademarks of Microware Systems Corporation.
  • Page 3 Although the information contained within this document is considered accurate and characteristic of the subject product, Performance Computer reserves the right to make changes to this document and any prod- ucts described herein to improve reliability, function, or design. Performance Computer does not assume any liability arising out of the application or use of any product or circuit described herein.

  • Page 4: Safety Information

    Safety Information This section is provided as a summary of the safety recommendations throughout this manual. Perfor- mance Computer (PCC) recommends that all safety precautions are followed to prevent harm to yourself or the equipment. Please follow all warnings marked on the equipment. Safety Precautions •...

  • Page 5: Table Of Contents

    Performance Computer Table of Contents Section 1 PT-VME161 INTRODUCTION ..........1 Scope ..........................1 Applicable Documents ..................... 2 Model Designations ....................3 Features ........................4 Family Members ......................6 PT-VME131/131E......................6 PT-VME141/141E......................7 PT-VME151A/151AE....................7 Glossary and Conventions ..................8 Glossary ........................
  • Page 6 Table of Contents SCSI device grounds .................... 24 Device addresses ....................... 25 Serial Port Cabling ....................25 Example........................25 Mechanical restraints....................26 Section 3 FUNCTIONAL DESCRIPTION ........... 27 Microprocessor ......................28 Memory ......................... 28 DRAM ......................... 28 DRAM Mapping..................... 29 Sizing ........................
  • Page 7 Performance Computer Local Level 7 Sources ..................39 Abort......................39 SCSI Bus Reset ..................40 AC Fail......................40 System Fail....................40 General Purpose Local Interrupts..............40 Location Monitor FIFO................40 SCV64 VME Event ..................41 Timer Event ....................41 Tick ....................... 41 Interval ....................
  • Page 8 Table of Contents SCSI DMA Parity Error ..................49 DARF Parity Error.................... 49 EPAK Parity Error .................... 50 SCSI Present ....................50 System Status Register 3..................50 DRAM Size ...................... 50 Parity Installed ....................50 Interval Timer Interrupt Pending ..............50 DUART ........................
  • Page 9 Performance Computer Interrupt Control ......................68 Register Maps ......................69 SCV64 ........................69 DS1643 Nonvolatile Timekeeping RAM ..............71 82C54 Interval Timer ....................71 EMULEX FAS216 SCSI Controller................72 68681 DUART ......................72 Controls and Indicators ..................73 Rotary Switch ......................73 “RUN”...
  • Page 10 Table of Contents The differences between the PT-VME161 and the VME151 ....... 90 SCV64 ........................90 Differences: ......................90 68060 Versus 68040 ....................91 The differences between the PT-VME151A and the VME151 ....92 Renamed Registers....................92 New Devices....................... 92 DRAM Sizing ......................
  • Page 11 Figure 10: Block Diagram...................... 27 Figure 11: Interval Timer Block Diagram................32 Figure 12: Timer Block Diagram.................... 41 Figure 13: PT-VME161 Front Panel Controls and Indicators ..........73 Figure 14: SCV64 Memory Map................... 100 Extensible Single Board Computer/Controller User’s Manual xi...
  • Page 12 List of Figures xii Extensible Single Board Computer/Controller User’s Manual...
  • Page 13 Performance Computer List of Tables Table 1: EPAK Caching Options ................... 46 Table 2: Memory Map ......................59 Table 3: Default VMEbus A24 Memory Map ................. 60 Table 4: Default VMEbus A32 Memory Map ................. 60 Table 5: Interrupt Request Summary ..................68 Table 6: SCV64 Register Map....................
  • Page 14 List of Tables xiv Extensible Single Board Computer/Controller User’s Manual...

  • Page 15: Section 1 Pt-Vme161 Introduction

    PT-VME161 facilities are presented. Section 1 Provides an introduction and general overview of the PT-VME161. It is intended as a quick summary of PT-VME161 features and provides a framework for the rest of the docu- ment.

  • Page 16: Applicable Documents

    Section PT-VME161 INTRODUCTION Applicable Documents VMEbus Specification Manual, Revision ANSI/IEEE STD 1014-1987, VMEbus International Trade Association (VITA). VITA; 10229 N. Scottsdale Road, Suite B; Scottsdale, AZ 85253. M68000 Family Programmer’s Reference Manual; M68000PM/AD; Motorola Incorporated, 1989. Motorola Literature Distribution; P.O. Box 20912; Phoenix, AZ 85036.

  • Page 17: Model Designations

    The PT-VME161 is available with a 50 MHz 68060 microprocessor or a 50 MHz 68EC060 (68060 without MMU or FPU). Additionally, the PT-VME161 has options of 4, 8, 16, 32 or 64 megabytes of main memory. Model designations are as follows:...

  • Page 18: Features

    PT-VME161 INTRODUCTION Features • MC68060 Thirty-Two Bit Microprocessor With Internal Cache and FPU PT-VME161 utilizes 50 MHz MC68060 MPU w/Memory Management Unit PT-VME161E utilizes 50 MHz MC68EC060 MPU w/o MMU or FPU MC68040-Compatible Integer Execution Unit MC68881/MC68882-Compatible Floating Point Unit...
  • Page 19 Performance Computer • General Purpose Local I/O 68681 DUART Dual RS-232 ASYNC Serial I/O ports w/Front Panel Interconnect 16-bit General Purpose Timer 128 Byte EEPROM • DS1643 Nonvolatile Timekeeping RAM 8184 Bytes of Nonvolatile SRAM Real-Time Clock with Integrated Crystal...

  • Page 20: Family Members

    EMULEX SCSI controller on the PT-VME161, PT-VME151 and PT- VME141 is a super set of the PT-VME131’s NCR SCSI controller. The MC68060 of the PT-VME161 is user code compatible with the MC68030 of the PT-VME131, PT-VME141 and PT-VME151. These and other design considerations were made to preserve your investment in code development.

  • Page 21: Pt-Vme141/141E

    MBytes per second. This high speed transfer capability makes the 141 ideal for applications that require maximum VMEbus utilization. The features of the PT-VME141 and PT-VME141E are identical to the PT-VME161 with the following exceptions: • Advanced Thirty-Two Bit Microprocessor With Internal Cache...

  • Page 22: Glossary And Conventions

    Section PT-VME161 INTRODUCTION Glossary and Conventions Glossary CPU - Central Processing Unit (MC68040 or MC68EC040) DMA - Direct Memory Access, hardware controller block data transfers. DMAC - Direct Memory Access Controller. DRAM - Dynamic Random Access Memory. longword - In this manual, this term indicates a 32-bit value.

  • Page 23: Conventions

    Performance Computer Conventions Upper case names enclosed in square brackets ([,]) represent signal names that can be found in the sche- matics. Numbers enclosed in “less than” (<) and “greater than” (>) symbols refer to individual bits of a signal bus.
  • Page 24 Section PT-VME161 INTRODUCTION 10 Extensible Single Board Computer/Controller User’s Manual...

  • Page 25: Section 2 Getting Started

    If no external damage is visible, carefully unpack contents from shipping carton, observing anti-static precautions identified above and verify against packing list. Inspect the PT-VME161 for any visible signs of shipping damage. If such physical damage is noted, report it immediately to Performance Tech- nologies or appropriate agent.

  • Page 26: Hardware Configuration

    GETTING STARTED Hardware Configuration A layout for the PT-VME161 is shown in “Figure 1: PT-VME161 Device Positions”. The model PT-VME161 and PT-VME161E are two versions of the same PCB with different component options. There are various jumpers to configure user options which must be set before initial bootup. Refer to the information in this section to verify that you have the correct settings.
  • Page 27 Performance Computer All Jumper Blocks are designed to mate with standard 2 pin jumper shunts. Spare jumper shunts can be stored by slipping one side of the jumper shunt on a single, unused pin of a jumper block and allowing the other side of the jumper shunt to hang in space.

  • Page 28: U24 Prom/Rom/Sram/Eeprom Socket Configuration

    Section GETTING STARTED U24 PROM/ROM/SRAM/EEPROM Socket Configuration Locations U24 and U36 both provide support for read only devices such as ROM, PROM, EPROM, and Flash EPROM. Location U24 has additional support for read/write devices as well, SRAM and non-vola- tile SRAM. The positions of locations U24 and U36 are identified in Figure 1: on page 12 and Figure 2: on page 14.

  • Page 29: Location U24 Setup

    Performance Computer Location U24 Setup Figure 3: K4 and K10Jumpers The pin out configuration for location U24 is defined by Jumper Blocks K4 and K10. There are eleven jumpers at location K4 and a single jumper at K10. Each K4 jumper position consists of a row of three adjacent pins. The Jumpers are numbered from 1 to 31 starting with Jumper 1 at the pin 1 end of the Jumper Block K4.

  • Page 30: Figure 5: U24 And U36 Jumper Settings

    Figure 5 displays Jumper Blocks K10, K4, K11, and K3 from the component side of the PCB. The pattern represented below is viewed when the PT-VME161 is placed on a work surface component side up and the Front Panel closest to the observer. “*” indicates factory configuration.

  • Page 31: Scsi Termination

    Terminator Fuse Disabling Termination If the PT-VME161 is not at one end of the SCSI cable then the termination will be supplied by another SCSI device and, SCSI Termination resistor packages RP1 and RP2 (shown above) must be removed. Termination Power Source The active termination circuit on the PT-VME161 draws its power from the SCSI TERMPWR signal pin.
  • Page 32 SCSIbus termination. The SCSI TERMPWR mechanism provided the solution. The PT-VME161’s +5V supply goes through fuse F1 then diode CR2 to be OR’ed into the SCSI TERMPWR signal. This allows the PT-VME161 to supply SCSIbus termination power when it is powered up and some other device on the SCSIbus to provide it when it is not.

  • Page 33: Dram Module Upgrading

    Optional EPAK PT-VME161 Base Module To install the new DRAM module, place the PT-VME161 on a work surface component side up. Care- fully align the bodies of the DRAM module connectors, and press firmly on top of the connector with both thumbs to snap it in.

  • Page 34: Epak Installation

    Section GETTING STARTED NOTE: All 3 standoffs must be properly installed because they are also used to carry power and ground to the DRAM Module. EPAK Installation If not already installed do it now! Follow the instructions contained in your EPAK User’s Manual. 20 Extensible Single Board Computer/Controller User’s Manual...

  • Page 35: Board Installation

    EPAK connector. +12V can also be used by EPROMS that require a VPP = 12V. Slot Considerations If you plan on using the System Controller functions of the PT-VME161 then it must be plugged into the Slot 1 position of the VME backplane. The System Controller functions will be automatically enabled after reset if the Slot 1 [BG3IN*] signal is open (or grounded).

  • Page 36: Figure 7: Pt-Vme161 Front Panel

    Section GETTING STARTED Figure 7: PT-VME161 Front Panel Captive Chassis Mount Screw PT-VME Ejector Handle System Status Indicators RESET Switch Rotary Switch ABORT Switch User Programmable LEDs Optional EPAK I/O Connector RS-232 Utility Port VME64 Ejector Handle Performance Technologies Captive Chassis Mount Screw...

  • Page 37: Scsi Considerations

    The PT-VME161 SCSI interconnect is provided through the User Defined Signal pins of the VMEbus P2 connector. The signals are organized so that a mass terminated Insulation Displacement Connectors (IDC) can be used to attach SCSI devices to the PT-VME161. See “Table 13: VMEbus” P2” Connec- tions” on page 77.

  • Page 38: Mechanical Restraints

    Section GETTING STARTED AMP 1-746288-0 (connector) AMP 499252-4 (strain relief) Figure 8: Example SCSI Cable 6 Meter Maximum A B C Pin 1 Indicator 50 Conductor Ribbon Cable 50 Pin Flat Cable Connectors for SCSI devices (up to 7) 64 Pin VMEbus “P2” Connector Mechanical restraints Depending upon your mechanical configuration, tie wraps or cable clamps may be necessary to provide mechanical support for the cable.

  • Page 39: Device Addresses

    Following is an example cable with vendors and part numbers for the components. These configurations have been tested at PTI. Figure 9 displays an example serial cable for the PT-VME161. The view is with the connector sockets pointing towards you.

  • Page 40: Mechanical Restraints

    Section GETTING STARTED Burndy FRS14BF-8 (strain relief included) or AMP 746288-2 (connector) AMP 499252-9 (strain relief) Figure 9: Example Serial port Cable 50 Foot Maximum Pin 1 Indicator 14 Conductor Ribbon Cable 14 Pin Flat Cable Connector 25 Pin D-Shell Connector Mechanical restraints Depending upon your mechanical configuration, tie wraps or cable clamps may be necessary to provide mechanical support for the cable.

  • Page 41: Section 3 Functional Description

    Section FUNCTIONAL DESCRIPTION A block diagram of the PT-VME161 is provided below. Down the center are the 32-bit microprocessor address and data busses. To the right is an 8-bit buffered data bus that provides I/O interface connectivity. To the left is the VMEbus interface, provided by the Advanced VMEbus Interface Chip Set.

  • Page 42: Microprocessor

    The 68060 and 68EC060 support a burst mode for filling their on-chip data and instruction caches. The PT-VME161 utilizes the fast page mode of the DRAM to accelerate the burst transfer operation. During a burst transfer four sequential long words are fetched from the DRAM, requiring four clock cycles for the first long word transfer and two clock cycles for subsequent long word fetches.

  • Page 43: Dram Mapping

    Performance Computer DRAM Mapping DRAM Size Address Range Response 4 MBytes 20000000-203FFFFFh Normal 20400000-20FFFFFFh Blank 21000000-213FFFFFh Normal - repeat of 20000000-203FFFFF 21400000-21FFFFFFh Blank The pattern of (4M Normal) - (12M Blank) - (4M Normal) - (12M Blank) repeats throughout the range of 20000000-2FFFFFFFh. Thus address 20000000h may be read or written at 21000000h, 22000000h, etc.

  • Page 44: Parity

    SCV64 or SCSI controller reference will assert the L7IMEM pin of the SCV64, gener- ating a level 7 interrupt request. The source of the a parity error is latched in PT-VME161 System Status Register 2. Parity errors that generate a Bus Error (68060 and EPAK bus masters) will not generate a Level 7 interrupt however, the source of the error will be latched in Status Register 2.

  • Page 45: Initialization

    Performance Technologies normally uses this memory to store various parameters and options used in the initialization and operation of the PT-VME161. This device is socketed so that it can be moved to another board if necessary. For instance, if board level replacement is typically performed on failures in the field, the EEPROM can be moved to the replace- ment board to maintain the configuration information of the original board.

  • Page 46: Interval Timer

    Section FUNCTIONAL DESCRIPTION Interval Timer The Interval Timer, an Intel 82C54, provides three independent 16-bit timers running off the same 4 MHz clock. These three timers are identical in operation. Refer to the Intel Peripherals Handbook for a complete description of the 82C54 When an Interval Timer is programmed in “Mode 2”, it will perform the following functions when it counts down to zero: pulse its OUTPUT pin, reload the initial count, and continue counting.

  • Page 47: Vmebus Interface

    The SCV64 is a 64-bit interface to the VMEbus address and data buses with the local PT-VME161 bus. It may act as a VMEbus Master or Slave. The local DRAM and EPAK address spaces of the PT-VME161 are accessible to a VMEbus Master through the SCV64. The SCV64 is also capable of DMA transfers between local memory (DRAM or EPAK) and the VMEbus.

  • Page 48: Atomic

    Section FUNCTIONAL DESCRIPTION the VMEbus handshaking rate. The receive and transmit FIFOs can be individually enabled using the RXATOM and TXATOM bits in the SCV64 Mode Control Register. The receive FIFO captures write transfers from VMEbus devices or DMAC VMEbus reads. Data can be moved into the FIFO using D64MBLT, D32BLT, D16BLT, or individual transfers.

  • Page 49: Vmebus Slave Accesses

    The Slave Image is the VMEbus address range throughout which the local memory of the board can be accessed. The slave image of the PT-VME161 is defined in programmable registers of the SCV64. Separate slave images, different in size, can be set up in the A64, A32 and A24 address spaces.

  • Page 50: Read-Modify-Write

    FFFFFFFFh. In order to access the full VMEbus address space the Page bit in the 161 System Control Register defines VMEbus address bit 31. When the Page bit is 0, PT-VME161 addresses 80000000h-FFFFFFFFh are mapped to VMEbus addresses 00000000h - 7FFFFFFFh.

  • Page 51: Location Monitor

    A32 and A24 slave images. The monitor is equally accessible by the VMEbus and the local CPU. A process on the PT-VME161 does not need to determine whether the process it’s sending a message to is local or not.

  • Page 52: Reset

    The Local Bus Timer is used to recover from unsuccessful local transfers (internal to the PT-VME161). If a Local Dtack [-KSA0] is not detected within 512 us. of the assertion of Local Data Strobe [- KDS] the SCV64 will assert Local Bus Error [-KBER] until the Local Data Strobe signal is released.

  • Page 53: Register Block

    In the case of multiple active interrupts on a level that is being acknowledged, auto-vector sources have the highest priority followed by local vectored interrupts and finally, VMEbus interrupts. Details of PT-VME161 use of the SCV64 interrupt inputs follows: Local Level 7 Sources On the SCV64 there are five interrupts dedicated to level 7: the internal BI-mode signal and the external L7INMI, L7IMEM, L7IACF and L7ISYF signals.

  • Page 54: Scsi Bus Reset

    If the VMEbus [ACFAIL*] signal is asserted an interrupt can be generated to the 68060. The AC Failure warning allows the PT-VME161 software to execute appropriate shut- down procedures. The interrupt is enabled by setting the ACFIS bit in the SCV64 Level 7 Interrupt Status Register.

  • Page 55: Scv64 Vme Event

    Performance Computer SCV64 VME Event This interrupt indicates that an event related to VMEbus use has occurred - such as DMA has finished or a bus error (SCV64 [-KBER] or VMEbus [BERR*]) has occurred. It is negated when the appropriate flags in the SCV64 status register are cleared.

  • Page 56: Interval

    Section FUNCTIONAL DESCRIPTION Interval The latched outputs of the individual Interval Timers may be cleared by writing the appropriate bit combinations to the RITI field of System Control Register 2. Interrupts from the three Interval Timers can be disabled by clearing the EITI bit (5) in System Control Register 2.

  • Page 57: Duart Interrupt Request (-Intp<5>)

    “vectored” or “auto-vectored” interrupt is presented to the 68060. The EPAK [-EPVIR] signal drives the SCV64 interrupt input pin -LIRQ4 through signal line [-INTP<4>]. CAUTION: Due to the PT-VME161 hardware implementation the “vectored” option must always be used for the SCV64 Local Interrupts 5 and 4 Control Register 4AV bit.

  • Page 58: System Monitor Functions

    SCV64 enables itself as the VMEbus System Controller. The System Controller functions will be enabled automatically if the PT-VME161 is in slot 1 and [BG3IN*] is open. Software can determine if this has occurred by reading the SYSC status bit of the SCV64 Status Register...

  • Page 59: Bus Timer

    System Control Register is used to define VMEbus address bit 31. When the VMEbus Page Select bit is 0, PT-VME161 addresses 80000000h-FFFFFFFFh are mapped to VMEbus addresses 00000000h - 7FFFFFFFh. When the VMEbus Page Select bit is 1, PT-VME161 addresses 80000000h-FFFFFFFFh are mapped to VMEbus addresses 80000000h-FFFFFFFFh.

  • Page 60: Scsi Dma Read/Write Direction

    DARF VMEBAR register is programmed to allow a A32 Slave Image Size greater than or equal to 32MBytes (Dh). In this case a portion of the PT-VME161 slave image is replaced by 46 Extensible Single Board Computer/Controller User’s Manual...

  • Page 61: Enable Epak Access From The Vmebus

    Performance Computer the EPAK’s address space. When EPAK Accesses from the VMEbus are disabled, all of the PT-VME161 installed DRAM may be Accessed by a VMEbus master. EEAV is cleared at reset, enable EPAK Access. EEAV is register bit 0.

  • Page 62: Enable Interval Timer Interrupts

    Section FUNCTIONAL DESCRIPTION Reset Interval Timer Interrupts The RITI bits are encoded to reset the Request Latch of the individual Interval Timers. When an Interval Timer reaches it’s terminal count, the event is recorded by its Request Latch. The outputs of the three Request Latches are OR’ed together, generating the Interval Timer Interrupt Request to the 68060.

  • Page 63: System Status Registers

    Performance Computer System Status Registers The System Status register provides the PT-VME161 with status information not provided in other regis- ters. It is a read only register. All unused bits (31-4) should be masked to zero (0) for future expansion.

  • Page 64: Epak Parity Error

    The DRAM Size field (named DRAMSZ) indicates the size of the DRAM module installed on the PT-VME161 base board. DRAMSZ is a three bit field. It consists of register bits 0 through 2, where bit 0 is the least significant bit. The following table elaborates the possible values:...

  • Page 65: Duart

    I/O. If you recieved a Performance Computer Debugger (PTBUG) as part of your order, Port A of the DUART will be set to 9600 baud, 1 stop bit, no parity. PTBUG ignores CTS and DTR and deasserts RTS and DSR (false).

  • Page 66: Epak General Purpose Input

    Section FUNCTIONAL DESCRIPTION EPAK General Purpose Input Parallel Input 3 of the DUART is attached to the EPAK +EPKIO signal. The state of this control signal can be read from the IP3 bit (3) of the DUART Input Port Register. The function of this pin is determined by the attached EPAK Expansion Module.

  • Page 67: Serial Eeprom Data Out

    Performance Computer Serial EEPROM Data Out Parallel Output 7 of the DUART is attached to the Data In (DI) pin of the 93C46 Serial EEPROM. Programmed I/O can control the state of this signal with OPR7 bit (7) of the DUART Output Port Register.

  • Page 68: Scsi Controller

    The SCSI interface is through the P2 VME connector. Termination is provided by optional plug-in resistor packs. The resistor packs should be installed if the PT-VME161 is at either end of a SCSI cable. Conversely, the resistor packs should be removed if the PT-VME161 is installed in the middle of the SCSI cable.

  • Page 69: Dma Mechanism

    Fuse F1 (Littelfuse Part No. 273-001) provides short circuit protection for TERMPWR. To remove the fuse, place the PT-VME161 on a work surface component side up with the VMEbus connectors closest to the observer. Grip the clear body of fuse F1 and pull to the right. To replace the fuse reverse the...
  • Page 70 Section FUNCTIONAL DESCRIPTION process. The bidirectional arrow in “Figure 6: SCSI Components” on page 17 shows the direction of motion. See “TERMPWR Overview” on page 17 for a discussion of the uses of TERMPWR. 56 Extensible Single Board Computer/Controller User’s Manual...

  • Page 71: Epak Interface

    Access to SRAM or registers on an EPAK. The EPAK may be Accessed form the VMEbus as part of the PT-VME161 address space. To do so, VMEbus address bit A24 must be 1, the EEAV bit in System Control Register 2 must be 0, and the A32SIZ field of the DARF VMEBAR register must be programmed to allow an A32 Slave Image Size greater than or equal to 32MBytes (Dh).
  • Page 72 Section FUNCTIONAL DESCRIPTION 58 Extensible Single Board Computer/Controller User’s Manual...

  • Page 73: Section 4 Functional Summary

    Section FUNCTIONAL SUMMARY Memory Map Table 2 describes the location of all configuration and operational registers of the PT-VME161 as seen by the MC68060. The sizing column indicates if the device supports data bus sizing. Table 2: Memory Map ADDRESS RANGE...

  • Page 74: Default Vmebus Slave Addressing

    VMEbus master. The A32SIZ field of the SCV64 VMEBAR register must be re- programmed to allow an A32 Slave Image Size greater than or equal to 32MBytes (Dh). Table 3 describes the default address map of the PT-VME161 as seen by a VMEbus master using A24 addressing.

  • Page 75: 161 System Registers

    Performance Computer 161 System Registers There are six registers on the PT-VME161 that are not defined in the referenced data sheets. These regis- ters are unique to the PT-VME161, providing control of major functional blocks and status. System Control Register 1...
  • Page 76 Section FUNCTIONAL SUMMARY Enable 68060 caching of VMEbus accesses. See “PT-VME151A Control Register Differences” on page 96 for in-depth discussion. Disable caching Enable caching 62 Extensible Single Board Computer/Controller User’s Manual...

  • Page 77: System Control Register 2

    Performance Computer System Control Register 2 Address 50000000h Byte Read/Write Only All bits cleared to zero by reset, except ETTI EEAV EPEC RITI EITI ETTI ESNP Name Function EEAV Enable EPAK Access from VMEbus Enable EPAK Access from VMEbus when A24 = 1...

  • Page 78: System Status Register 1

    SRAM Size No SRAM installed Reserved, mask to zero when read The PT-VME161 does not support SRAM so this field is always read as zero. This provides backwards compati- bility with the PT-VME151. 64 Extensible Single Board Computer/Controller User’s Manual...

  • Page 79: System Status Register 2

    Performance Computer System Status Register 2 Address 60000000h Byte Read Only Reserved 60PE SCSIPE DARFPE EPAKPE SCSIP Reserved Name Function Reserved, mask to zero when read 60PE 68060 Parity Error A parity error was detected during a 68060 DRAM read...

  • Page 80: System Status Register 3

    Section FUNCTIONAL SUMMARY System Status Register 3 Address 68000000h Byte Read Only DRAMSZ PARI ITIP0 ITIP1 ITIP2 Reserved Name Function DRAMSZ Indicates the amount of DRAM installed Reserved 64 Meg 32 Meg 16 Meg 8 Meg 4 Meg PARI Parity Installed Parity generation and checking logic installed Parity logic not installed - no parity errors generated ITIP0...

  • Page 81: Scsi Memory Address Register

    The SCSI Memory Address Register is written with the starting address for a SCSI DMA transfer. The register retains its value after reset and is unde- fined after power up Jumper List (Defaults) This section provides a summary of the jumpers on the PT-VME161 and their default settings. JUMPER DEFAULT FUNCTION...

  • Page 82: Interrupt Control

    Section FUNCTIONAL SUMMARY Interrupt Control The SCV64 controls local and VMEbus interrupts. Because the SCV64 allows the dynamic assignment of local interrupts to specific request levels, a fixed interrupt map is unnecessary. The following table lists the internal and VMEbus interrupt sources and the levels to which they may be assigned. The SCV64 interrupt input pin for each local interrupt request is also shown.

  • Page 83: Register Maps

    Performance Computer Register Maps The “INIT” column in the register map descriptions below identify the initial register values typically programmed by PTI for our applications. All “INIT” values are in hexadecimal, registers that are “don’t care” at initialization time contain a hyphen.
  • Page 84 * Initialized by PTBUG. If PTBUG is not used, DLCT must be initialized by the user with their own EPROM code or in some other fashion. Also see Appendix F “Mode Register Initialization”, on page 91. ** Not accessible by the PT-VME161. 70 Extensible Single Board Computer/Controller User’s Manual...

  • Page 85: Ds1643 Nonvolatile Timekeeping Ram

    Performance Computer DS1643 Nonvolatile Timekeeping RAM Table 7: DS1643 Nonvolatile Timekeeping RAM Registers ADDRESS FUNCTION VALUES INIT 0F000000h- Nonvolatile RAM User Definable 0F001FF7h 0F001FF8h Control Register 0F001FF9h Seconds 00-59 msb = 0 0F001FFAh Minutes 00-59 0F001FFBh Hours 00-23 0F001FFCh 01-07...

  • Page 86: Emulex Fas216 Scsi Controller

    Section FUNCTIONAL SUMMARY EMULEX FAS216 SCSI Controller Table 9: EMULEX FAS216 SCSI Controller Register Map ADDRESS READ FUNCTION WRITE FUNCTION INIT 0A000000h Transfer Counter Low Transfer Count Low 0A000001h Transfer Counter Mid Transfer Count Mid 0A000002h FIFO FIFO 0A000003h Command Command 0A000004h Status...

  • Page 87: Controls And Indicators

    Performance Computer Controls and Indicators The figure below identifies the controls and indicators that reside on the PT-VME161 Front Panel. Figure 13: PT-VME161 Front Panel Controls and Indicators PT-VME “RUN” Indicator “FAULT” Indicator “VME” Indicator RESET Switch Rotary Switch ABORT Switch...

  • Page 88: Run" Indicator

    This green indicator is illuminated during the period of a VMEbus master access attempt. The LED illu- mination intensity is a relative indication of the PT-VME161’s VMEbus access frequency. A solid, bright light is indicative of high bus contention where the PT-VME161 is not receiving a Bus Grant. RESET Switch The reset switch is a red push button on the front panel which is tied to the EXTRST input pin of the ACC which in turn generates a board reset [-LRST].

  • Page 89: Section 5 Connector Pinouts

    Section CONNECTOR PINOUTS Utility Serial Port Pin Assignments Connections to the Debug/Utility port can be made using the supplied cable. A Data Terminal Equipment RS-232C interface is provided. A transition cable is supplied which converts between the 14-pin header (P3) and a female shell (male pin) 25-pin D-Shell connector. Table 11: Utility Serial Port Pin Assignments DB 25 Pin Circuit...

  • Page 90: Vmebus Pin Assignments

    Section CONNECTOR PINOUTS VMEbus Pin Assignments Table 12: VMEbus “P1” Connections Signal Signal Signal BBSY* BCLR* ACFAIL* BG0IN* BG0OUT* BG1IN* BG1OUT* BG2IN* BG2OUT* SYSCLK BG3IN* SYSFAIL* BG3OUT* BERR DS1* BR0* SYSRESET* DS0* BR1* LWORD* WRITE* BR2* BR3* DTACK* IACK* IACKIN* IACKOUT* IRQ7* IRQ6*...

  • Page 91: Table 13: Vmebus" P2" Connections

    VRMC* TPWR VMEbus P2 connector rows A and C are User Definable connector pins. The PT-VME161 provides the connections identified above for the SCSIbus interconnect. NOTE: VRMC* is a jumper (K7) selectable option. The IEEE 1014 Rev C VMEbus Specification defines this signal as “RESERVED”.

  • Page 92: Epak Connectors

    Section CONNECTOR PINOUTS EPAK Connectors The PT-VME161 EPAK module interface is comprised of connectors J1, J2, and J3, and the six EPAK standoffs. Table 14: EPAK Connections Signal Signal Signal +MPSZ0 +MPA24 +MPSZ1 +MPA25 +MPFC0 +MPA26 +MPA00 +MPFC1 +MPA27 +MPA01...

  • Page 93: Dram Module

    Performance Computer The EPAK mounting standoffs are used to carry power and ground to the EPAK module. Table 15: EPAK mounting standoffs Mounting pin Signal DRAM Module The DRAM Module standoff carries ground to the module.] Table 16: DRAM Module Connections...

  • Page 94: Table 17: Epak Mounting Standoffs

    Section CONNECTOR PINOUTS Table 16: DRAM Module Connections Signal Signal RAS2 RAS3 PTST RASP The DRAM mounting standoffs are used to carry power and ground to the DRAM module. Table 17: EPAK mounting standoffs Mounting pin Signal 80 Extensible Single Board Computer/Controller User’s Manual...

  • Page 95: Section 6 Mechanical And Environmental

    Section MECHANICAL AND ENVIRONMENTAL Power Requirements The following values are without an EPAK installed. Table 18: Power Requirements Voltage Typical Maximum +5V (±5%) 3.9 Amps 4.4 Amps +12V (±5%) 25 mA 42 mA -12V (±5%) 25 mA 42 mA Ambient Temperature Table 19: Ambient Temperature Minimum Maximum...

  • Page 96: Mechanical Shock

    Section MECHANICAL AND ENVIRONMENTAL Mechanical Shock Designed to meet 20g for 6 ms (half sine). Physical Dimensions Base board only Table 21: Physical Dimensions Dimension Millimeters Inches Width Depth Front Panel 20.3 Component Height 82 Extensible Single Board Computer/Controller User’s Manual...

  • Page 97: Section 7 Appendices

    APPENDICES APPENDIX A: Product Warranty Performance Computer, A Performance Technologies Company (hereinafter “PCC”) warrants that its products sold hereunder will at the time of shipment be free from defects in material and workmanship and will conform to PCC’s applicable specifica- tions or, if appropriate, to Buyer’s specifications accepted by PCC in writing.

  • Page 98: Product Return Procedure

    Section APPENDICES APPENDIX B: Product Return Procedure If you find that your Performance Computer (“PCC”) product must be returned for repair, note the following: To return equipment, please obtain a Return Material Authorization (RMA) number. PCC cannot accept returns without an RMA number.

  • Page 99: Product Support

    8:00 am and 5:00 pm Eastern Time, Monday through Friday. In addition, Performance Computer supports an internet mail server. This can be used to get updated drivers and other information on PCC’s products, You can request a usage document by sending electronic mail to the server, with nothing in the body of the email text (no signature files).

  • Page 100: Installation Notes

    SENSITIVE TO STATIC ELECTRICITY. ORDINARY AMOUNTS OF STATIC ELECTRICITY GENERATED BY YOUR CLOTHING OR WORK ENVIRONMENT CAN DAMAGE THE ELEC- TRONIC EQUIPMENT. IT IS RECOMMENDED THAT WHEN INSTALLING THE PT-VME161 IN A SYSTEM OR THE COMPONENTS ON THE BOARD ITSELF THAT ANTI-STATIC GROUNDING STRAPS AND ANTI-STATIC MATS ARE USED TO HELP PREVENT DAMAGE DUE TO ELECTROSTATIC DISCHARGE.

  • Page 101: Eeprom Usage

    The SCV64 requires that a reference to the location monitor be performed before it will respond as a slave to shared memory accesses. Byte location 1Eh contains a flag that determines whether the PT-VME161 will make this reference to itself (requiring that it accesses the VMEbus immediately after reset) or allows an appropriate driver make the initial reference.

  • Page 102: Table 22: Eeprom Default Values

    PTI offers the OS-9 Real-Time Operating System from Microware Systems Corporation for the PT-VME161. Locations 44h through 63h are used by OS-9 if installed. For more information contact PTI or Microware. Address: Microware Systems Corporation; 1900 N. W. 114th Street; Des Moines, Iowa 50325.
  • Page 103 Performance Computer Table 22: EEPROM Default Values Address Length Default Description 1 byte Floppy Format 8 bytes “shell” Shell String 2 bytes $0400 Number Of 256 Byte RAM Disk Sectors 2 bytes $0000 SCSI Master/Slave Boot (Slave) 6 bytes XX XX XX...

  • Page 104: The Differences Between The Pt-Vme161 And The Vme151

    APPENDIX F: The differences between the PT-VME161 and the VME151 It may be desirable to run software written for the PT-VME151/151A on a PT-VME161. Most of the new features on the 161 are disabled after reset, making them transparent to existing software. This appendix is an overview of the programming issues that must be considered when porting code from the PT- VME151A/151AE to the PT-VME161.

  • Page 105: 68060 Versus 68040

    Performance Computer Mode Register Initialization - Initialization code must set the BUSSIZ and SWAP bits of the SCV64 Mode Register (address $1800003C) to 1. These bits are set by PTBUG upon reset; initialization code written by the user must set these bits. These bits were set automatically in the VME151/151A.

  • Page 106: The Differences Between The Pt-Vme151A And The Vme151

    NOTE: The following Appendix has been provided for customers that are upgrading from a PT- VME151 to the PT-VME161. Information in this Appendix must be used to change native PT- VME151 code to PT-VME151A code before applying changes needed for the PT-VME161.

  • Page 107: Sram Access

    Performance Computer As an alternative to the memory sizing algorithms required by the 151, the 151A System Status Register 2 provides DRAM size information. See “System Status Register 3” on page 66 for list of the encoded values. SRAM Access The PT-VME151A does not support the SRAM option that was available on the 151.

  • Page 108: Pt-Vme151A Differences From Vme131/141

    NOTE: The following Appendix has been provided for customers that are upgrading from a PT- VME131/141 to the PT-VME161. Information in this Appendix must be used to change native PT- VME131/141 code to PT-VME151A code before applying changes needed for the PT-VME161.

  • Page 109: 68040 Cache Control Registers

    Performance Computer many read cycles can be performed internal to the chip while the longer external write cycles are executing. Address spaces where writes and reads may be out of sequence with respect to each other are said to be nonserialized. Note that reads are performed in the order found in the code and writes are also performed in order.

  • Page 110: 68040 Cache Clearing

    Section APPENDICES 68040 Cache Clearing NOTE: The user should note that the 68040 caches are disabled after a reset but are not cleared or invalidated. The user needs to explicitly clear the instruction and data caches using the CINV instruction as part of initialization. 68040 Exception Processing NOTE: The user should note that 68040 exception processing differs from that of the 68030.
  • Page 111 Performance Computer discarding the data it doesn’t need. This could have adverse effects on VMEbus bandwidth since the PT- VME151A could be doing four times as many reads as it needs. If this situation occurs, the only solutions are to disable all data caching (using the 68040 Cache Control Register) or to use the MMU of the 68040 to make VME space noncacheable.

  • Page 112: Scv64 Overview

    Section APPENDICES APPENDIX I: SCV64 Overview The SCV64 contains functions such as a VMEbus requester, arbiter, interrupter and system controller (VMEbus System Controller functions are automatically provided when internal circuitry detects that the host card is installed in slot 1), and functions related to internal operation such as an interrupt handler, tick timer and watchdog circuit.

  • Page 113: Location Monitor

    Performance Computer Location Monitor The location monitor is a specialized function of the SCV64 to assist in inter-processor communica- tion. It is a 32-bit wide, 31-entry deep message FIFO loaded from the data bus when the location monitor is written to, so that either 16- or 32-bit messages or memory pointers can be sent between processes.

  • Page 114: Figure 14: Scv64 Memory Map

    Section APPENDICES Figure 14: SCV64 Memory Map FFFFFFFFh Page 31 A16:D16 Location 64 KBytes FFFF0000h Page 30, A32:D32 Page 29, A32:D32 Page 28, A32:D32 96 MBytes Page 27, A32:D32 Less A32:D32 Space 64 KBytes Page 26, A32:D32 Page 25, A32:D32 Page 24, A32:D32 FA00FFFFh Page 23, A32:D32...

  • Page 115: Master Vmebus Accesses

    Performance Computer The A16:D16 region is located at the top of the memory map, in the last 64Kb (FFFF0000h- FFFFFFFFh). This space can be disabled using the A16DI bit in the SCV64 Mode Control Register, in which case that address range becomes A32:D32. If the A16 region is enabled and the CPU accesses that region, the SCV64 will perform the cycle on the VMEbus with address bits 31 through 16 set to one, and will use the address modifier codes indicating short addressing.

  • Page 116: Slave Vmebus Accesses

    Section APPENDICES The transmit and receive channels of the SCV64 can each be programmed to operate in atomic or decoupled mode by using the RXATOM and TXATOM bits in the SCV64 Mode Control Register. Read cycles and interrupt acknowledge cycles are always atomic. In atomic mode accesses, the CPU transfer is not queued by the transmit FIFO;...
  • Page 117 Performance Computer SCV64, the same memory locations are selected. Otherwise, it is possible that different areas of local memory could be accessed through those three paths. The restriction on the slave image base is that it must be a multiple of the amount of memory installed on the CPU card.

  • Page 118: Avics Application Notes

    L7I0) interrupts can be masked. All interrupts are autovectored, except for LIRQ4 and LIRQ5 which can be programmed to be vectored or autovectored. Example: The following interrupt assignments are recommended for a PT-VME161 board: Table 25: Recommended Interrupt Assignments Signal Source*...

  • Page 119: Setting Up The Master Bus Memory Map

    Performance Computer Setting Up the Master Bus Memory Map When the host accesses the VMEbus, the address used by the CPU determines the address and data modes the SCV64 will use to perform the cycle. All outgoing VMEbus accesses are affected by a programmed memory map.

  • Page 120: Example A

    Section APPENDICES CAUTION: The A24 base address must be a multiple of the amount of memory installed on board. Step 2 Select the desired address protection boundary by entering the required value into SCV64 Access Protect Boundary Register. Step 3 Set the A24SLVEN bit (located in the SCV64 Mode Control Register) if an A24 image is desired;...

  • Page 121: Example B

    Step 7 Clear the VPG bit of the PT-VME161 System Control Register (address $0D000000) to select access of lower 2GB VMEbus space. Write the value 0 (word or longword only) to address 883FFFFCh, disabling BI-mode by writing to the location monitor (with bit 31 of the address set).

  • Page 122: Generating Vmebus Interrupts

    Section APPENDICES another board can get at the location monitor in A24 space at any address with a valid A24 address modifier. Step 8 Do a dummy read from SCV64 Location Monitor FIFO Read Port to clear the previous location monitor entry. Step 9 Read the BI bit of SCV64 Status Register 1 to make sure it's cleared.

  • Page 123: Initiating A Dma Transfer

    Performance Computer Initiating a DMA Transfer Step 1 Make sure the system is not in BI-mode (refer to steps 7-9 of “Setting Up A24/A32 Slave Images on the Bus” on page 105). Step 2 Set the VINEN bit (located in the SCV64 Mode Control Register) to enable SCV64 func- tions.
  • Page 124 Section APPENDICES Step 6 Set the DMA24 bit of SCV64 Mode Control Register to enable the DMA to operate as an A24 master. Step 7 Write 200h to SCV64 DMA Transfer Count Register to perform 512 longword transfers (2 Kbytes). Step 8 Clear TXATOM bit of SCV64 Mode Control Register to put tx FIFO into decoupled mode.

  • Page 125: Vmebus Address Modifiers

    Performance Computer APPENDIX K: VMEbus Address Modifiers VMEbus Address Modifier is a 6 bit field that is presented on the VMEbus Address Modifier signal lines during data transfer cycles. This table provides a quick summary of the Address Modifier codes. All values in hex.
  • Page 126 Section APPENDICES 112 Extensible Single Board Computer/Controller User’s Manual...
  • Page 127 Section SCHEMATICS Signal name cross references are available upon request. Extensible Single Board Computer/Controller User’s Manual 113...
  • Page 128 Section SCHEMATICS 114 Extensible Single Board Computer/Controller User’s Manual...
  • Page 129 Section INDEX Symbols +EPKIO ........................51, 52 Numerics 68040 see - MC68040 82C54 ........................59, 71 A64 Addressing ......................33, 36 A64, A32, A24, A16 see - VMEbus, Address Modifiers Control and Status Register TICKM ......................38 General Control Register LTOEN ......................38 SBI ........................106 SWRST ......................8, 44 TLEN0 ......................38 TLEN1 ......................38...
  • Page 130 Section L3E ........................42, 55 L4E ........................42 L5E ........................43 Local Interrupt Status Register LI1........................41 LI2 .........................39, 41 LI3 .........................42, 55 LI4 .........................42 LI5 .........................43 Local Interrupts 1 and 0 Control Register ............104 1L1-1L0 ......................41 Local Interrupts 3 and 2 Control Register ............104 2L2-2L0 ......................41 3L2-3L0 ......................42 LIRQ2 ......................39...
  • Page 131 Performance Computer BG3IN* ........................44 BI-mode see - DARF64, BI-mode Caching ........................94 CTS ...........................51 D64MBLT description ......................33 DARF VMEbus Slave Base Address Register A32SIZ ......................46, 57 DARF64 68040 considerations ..................94 Access Protect Boundary Register ..............103, 106 address modifiers ....................35 BI-mode ......................98, 101, 106 Control and Status Register BARDY ......................102, 106...
  • Page 132 Section A24DI ......................101, 105 A24P0 ......................105 A24PO ......................101, 105, 109 A24SLVEN ....................106 BLEN ......................36, 37 BLT .......................109 DARFEN ......................109 DMA24 ......................109 DMABEN .....................34, 36 DMAD16 ......................109 DMARD ......................109 FIFOBEN ......................34, 36 LPBK ......................37 MBLT ......................109 NOREL ......................37 PROT ......................103, 106 RXATOM .....................34, 102, 103 TXATOM .....................34, 102, 109 VINEN ......................102, 103, 106...
  • Page 133 Performance Computer interrupt setup .....................40 Output Port Register OPR0 ......................52 OPR1 ......................52 OPR3 ......................52 OPR5 ......................52 OPR6 ......................52 OPR7 ......................53 EBOARD ........................57 EEPROM, serial ......................31, 52, 53 EPAK ........................42, 57, 59 address space .......................46, 96 EPIRQ .........................42 installation ......................20 Interrupt Request ....................42 interrupt setup .....................40...
  • Page 134 Section Status Register INT ........................42 Flash EPROM ......................31 configuration .......................14 front panel .........................73 Abort button ......................39 hexadecimal switch .....................49 indicators ......................74 Reset button ......................38 User LEDs ......................45 hexadecimal notation ....................8 Initialization requirements ..................95 inter-processor communication see - Location Monitor ..................99 Interval Timer ......................71 Interrupt Request ....................41 JEDEC Devices ......................14...
  • Page 135 Performance Computer positions ......................12 summary ......................67 Local Reset .......................38, 45, 46 Location Monitor ......................99 access ........................106 default address ....................60 longword data types ....................8 Main Memory ......................59 burst mode ......................36 MC68040 ........................28 8-bit I/O considerations ..................95 auto-vector interrupts ..................40, 43 burst mode ......................28 Bus Error - DRAM Parity ...................30...
  • Page 136 Section OS9 ...........................51 Parity .........................30 PROM ........................31 configuration .......................14 PTBUG ........................51, 60 DRAM ........................28 Write Protected .....................60 Initialization ......................31 Nonvolatile EEPROM ......................31 SRAM ......................31, 59 Timekeeping ....................31 Parity ........................30 SRAM .........................31 read-modify-write cycles ..................101 Register Maps ......................69 reserved fields ......................8 ROM .........................31 configuration .......................14 RS-232 ........................51...

  • Page 137: Section 8 Schematics

    Performance Computer TERMPWR ......................17 Overview .......................18 SCV64 ........................59, 69 serial number location ....................11 Serial Port cabling .........................25 setup, see DUART signal name conventions ...................9 SRAM ........................31 configuration .......................14 SRAM Module installation ......................19 pin assignments ....................79 SYSCLK ........................44 SYSFAIL* ........................40 SYSRST* ........................38, 44 System Control Register 1 ..................45, 59, 61...
  • Page 138 Section TERMPWR .......................55 Timer General Purpose ....................51 Interval ........................32 Interrupt Request ...................32 Local Bus ......................38 RTC ........................31 Tick ........................38 Interrupt Request ...................39 Timekeeping RAM .....................31 VMEbus Data Transfer ..................45 VMEbus Mastership ...................35, 43 Watchdog ......................38 Utility Serial Port connections ......................75 see DUART VME64 features ........................33...
  • Page 139 Performance Computer Interrupt handler ....................39 interrupts ......................43, 68 memory map .......................99 ownership timer ....................43 P2 Connector .......................54 Page Selection .....................46 Pin assignments ....................76 Read-Modify-Write ....................36 Release on Request (ROR) .................43 Release when Done (RWD) ................43 setup ........................107 slave image ....................102, 103, 105, 106 Slot selection .......................21...
  • Page 140 Section 126 Extensible Single Board Computer/Controller User’s Manual...

Table of Contents