System Status Registers; System Status Register; Hex Switch; 68040 Parity Error - Performance Computer PT-VME151A User Manual

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Section FUNCTIONAL DESCRIPTION

System Status Registers

The System Status register provides the PT-VME151A with status information not provided in other
registers. It is a read only register. All unused bits (31-4) should be masked to zero (0) for future expan-
sion.
This register should only be referenced using byte operations. Reading it as a word or longword will be
translated into multiple byte reads by the sizing logic, with the same data byte being repeated on each
reference.

System Status Register 1

System Status Register 1 is an 8-bit, read only register. This register resides at location 0C000000h.

Hex Switch

System Status Register 2
System Status Register 2 is an 8-bit, read only register. This register resides at location 60000000h.

68040 Parity Error

SCSI DMA Parity Error

DARF Parity Error

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The current setting of the front panel hexadecimal switch can be read through this register. The
hex switch value will be presented as a nibble on data bits 3-0 at location 0C000000h (bit 0 is
the least significant bit). This four bit field is referred to as HSW.
When the 68040 Parity Error bit (named 040PE) is read as 1, it indicates that a parity was
detected during a 68040 DRAM read cycle. Notification of the error is though a Bus Error that
is generated as a acknowledgment on the DRAM reference. The Bus Error Handler must check
this bit to determine if bad DRAM parity was the source of the Bus Error. 040PE is cleared by
reset and after each time System Status Register 2 is read. 040PE is register bit 1.
When the SCSI DMA Parity Error bit (named SDMAPE) is read as 1, it indicates that a parity
was detected during a SCSI DMA DRAM read cycle. Notification of the error is though a level
7 Interrupt to the 68040 that is generated immediately after the DRAM reference in error. The
Level 7 Interrupt Handler must check this bit to determine if bad DRAM parity was the source
of the interrupt. SDMAPE is cleared by reset and after each time System Status Register 2 is
read. SDMAPE is register bit 2.
When the DARF Parity Error bit (named DARFPE) is read as 1, it indicates that a parity was
detected during a DARF DRAM read cycle. Notification of the error is though a level 7 Interrupt
to the 68040 that is generated immediately after the DRAM reference in error. The Level 7
Interrupt Handler must check this bit to determine if bad DRAM parity was the source of the
interrupt. DARFPE is cleared by reset and after each time System Status Register 2 is read.
DARFPE is register bit 3.