Vmebus Page Select; User Leds; Scsi Dma Read/Write Direction; Epak Space Cache Enable - Performance Computer PT-VME151A User Manual

3
Section FUNCTIONAL DESCRIPTION

VMEbus Page Select

User LEDs

SCSI DMA Read/Write Direction

EPAK Space Cache Enable

VMEbus Space Cache Enable

46 Extensible Single Board Computer/Controller User's Manual
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Access to the VMEbus address space is through the local addresses 80000000h-FFFFFFFFh. In
order to access the full VMEbus address space, the VMEbus Page Select bit (VPG) in the
System Control Register is used to define VMEbus address bit 31. When the VMEbus Page
Select bit is 0, PT-VME151A addresses 80000000h-FFFFFFFFh are mapped to VMEbus
addresses 00000000h - 7FFFFFFFh. When the VMEbus Page Select bit is 1, PT-VME151A
addresses 80000000h-FFFFFFFFh are mapped to VMEbus addresses 80000000h-FFFFFFFFh.
Local Reset clears (0) this bit.
There are four LEDs on the front panel (D3, D2, D1, and D0) that are under program control.
Writing a one to the LED3-LED0 bits in the System Control Register will light the respective
LED. When Local Reset is asserted all the four LEDs will be turned off.
SDIR in the System Control Register determines the direction of a data transfer during a SCSI
DMA operation. Setting this bit will generate data movement from DRAM to the FAS216, a
write to the SCSI bus. Clearing it moves data from the FAS216 to DRAM, a read from the SCSI
bus. Local Reset clears (0) this bit (SCSI DMA Read).
The ability to cache information in the EPAK address space (30000000h-3FFFFFFFh) is deter-
mined by the MC68040 Transparent Translation Registers. This makes the Enable EPAK
Caching bit of the Control Register irrelevant. Below are the possible combinations of events:

Table 1: EPAK Caching Options

68040 DTTR
EPAK Cache Enable
Disabled
Enabled
Enabled
Local Reset clears (0) this bit, enabling caching. See "APPENDIX F: PT-VME151A Differ-
ences From VME131/141" on page 91 for an in-depth discussion of EPAK caching.
Reads from the VMEbus address (80000000h-FFFFFFFFh) space can be cached. When the
VCE bit in the System Control Register is cleared (0) VMEbus space caching is enabled. When
set (1) it is disabled. Local Reset clears (0) this bit, enabling caching.
With respect to VME memory space, VME space is not explicitly affected by the mapping of
the MC68040 Transparent Translation Registers (discussed in "PT-VME151A Control Register
Differences" on page 93). Therefore, the VME Caching Enable bit in the System Control
Register still controls the cacheability of VME address space.
VME151 Control Register
EPAK Cache Enable
Don't Care
True
False
EPAK Caching?
No (Normal mode)
Yes
No, but 4 lwords fetched