Tick Timer; Register Block; Interrupt Handler; Local Level 7 Sources - Performance Computer PT-VME151A User Manual

before the 2 seconds delay expires results in the assertion of Local Reset [-LRST]. Local Reset
initializes the 68040 and all I/O devices on the PT-VME151A.
The Watchdog Timer can be disabled by jumper K1.

Tick Timer

The Tick Timer is a user programmable timer in the ACC. It can be set to one of two different modes
by the TICKM bit in the ACC Control and Status Register: normal or fast. In normal mode, the
interval can be set to 5, 10, 50, or 100 ms. In fast mode, the interval can be set to 0.2, 0.4, 2.0, or 4.0
ms. The intervals are selected by the TLEN1 and TLEN0 bits in the ACC General Control Register.
The TICK pin of the ACC is asserted (driven low) each time the timer expires and remains asserted
until software resets it via the CLRTIK bit in ACC Status Register 0.
Assertions of the TICK pin are at multiples of the selected interval, not a new interval from the 0 to
1 transition of CLRTIK.
The TICK pin generates the Tick Timer Interrupt Request through the LIRQ2 pin of the ACC. The
Tick Timer Interrupt Request can be disabled by setting the ETTI bit (6) in System Control Register
2. The current state of the TICK pin can be determined by reading the ITIP bits in System Status
Register 3 and the LI2 bit in the ACC Local Interrupt Status Register. If LI2 is asserted (1 = asserted)
and ITIP0, ITIP1, and ITIP2 are all negated (0) then a Tick Timer Interrupt Request is pending. After
reset, the Tick Timer Interrupt Request is enabled, maintaining compatibility with PT-VME151.
An interrupt on the LIRQ2 pin can be programmed (in the ACC Local Interrupts 3 and 2 Control
Register) to generate an auto-vector operation on any one of the 68040's seven interrupt request
levels. See "Timer Event" on page 41.
This timer is not used by any PTI supplied software or firmware.

Register Block

The ACC is a byte wide device with 16 directly addressable internal registers. Status bits, such as
active interrupts, are generally sampled by the ACC at the start of a register access cycle to ensure
stable data for the reference. Control bits with the exception of INT on the VMEbus Interrupter
register, are always stable. Detailed descriptions of the registers are available in the AVICS Tech-
nical Manual. A summary is provided in the Appendix.

Interrupt Handler

The ACC Interrupt Handler prioritizes interrupts from dedicated local level 7 sources, general
purpose local sources and the VMEbus. The Interrupt Handler also allows each source to be individ-
ually enabled, each of the six general purpose sources to be mapped to any of the seven interrupt
levels and the status of any local interrupt to be read.
In the case of multiple active interrupts on a level that is being acknowledged, auto-vector sources
have the highest priority followed by local vectored interrupts and finally, VMEbus interrupts.
Details of PT-VME151A use of the ACC interrupt inputs follows:

Local Level 7 Sources

On the ACC there are five interrupts dedicated to level 7: the internal BI-mode signal and the
external L7INMI, L7IMEM, L7IACF and L7ISYF signals. On the schematics ACC symbol the
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Extensible Single Board Computer/Controller User's Manual 39
Performance Computer