Acc; Reset; Local Bus Timer; Watchdog Timer - Performance Computer PT-VME151A User Manual

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Section FUNCTIONAL DESCRIPTION
image by the CPU does not go directly to memory, but goes out on the VMEbus then back in again
through the FIFOs. The VMEbus address and data transceivers drive the cycle onto the VMEbus,
but the DARF64 loads the cycle into its receive FIFO from its own I/O pads. The loopback acquires
mastership of the VMEbus for the process but the data read back through the Receive FIFO Address,
Data, and Receive Registers does not pass through the VMEbus buffers.
If a Bus Error [BERR*] occurs during a write to the VMEbus the VBERR bit in the Control and
Status Register is set, asserting the VMEINT pin. The Transmit FIFO Data, Address, and Control
Registers will contain the respective information for the bus cycle in error. When the VBERR bit is
cleared the DARF64 resumes with the next cycle in the FIFO.
If a Local Bus Error [-KBER] occurs during a write from the VMEbus the LBERR bit in the Control
and Status Register is set, asserting the VMEINT pin. The Receive FIFO Data, Address, and Control
Registers will contain the respective information for the bus cycle in error. When the VBERR bit is
cleared the DARF64 resumes with the next cycle in the FIFO.

ACC

The ACC (Advanced VMEbus System Architecture Control Circuit) provides the control logic for the
AVICS 64. The functions of the ACC are separated into several distinct modules. Some of these modules
provide hardware controlled service functions and have little interaction with system software. The
remaining modules can be configured by software to operate in various modes. They are accessed via the
Register Block.

Reset

The Reset block provides control of the PT-VME151A local reset signal [-LRST]. Local Reset is
asserted when the PT-VME151A detects a power on condition, if VMEbus [SYSRST*] is asserted,
the front panel Reset button is pressed, the watchdog timer expires, or software sets the SWRST bit
in the ACC General Control Register.
Local Reset will also be asserted if the ACC is the VMEbus System Controller and VMEbus
[BG0IN*] is asserted.

Local Bus Timer

The Local Bus Timer is used to recover from unsuccessful local transfers (internal to the PT-
VME151A). If a Local Dtack [-KSA0] is not detected within 512 us. of the assertion of Local Data
Strobe [- KDS] the ACC will assert Local Bus Error [-KBER] until the Local Data Strobe signal is
released. The timer duration is not user programmable, however it can be disabled by the control bit
LTOEN in the ACC General Control Register.
References to UNASSIGNED addresses on the Local Bus will not generate Local Dtack, requiring
the time-out mechanism for recovery. If the timer is disabled and such a condition occurs, the CPU
will hang. It is recommended that the timer only be disabled in a system development environment.
The timer is automatically enabled after the assertion of reset.

Watchdog Timer

The Watchdog Timer can be used to recover from software failures. The timer's 2 seconds delay is
restarted automatically by the release of Power On Reset [-PRST] and under program control by 0
to 1 transition of the CLRDOG bit in ACC Status Register 0. Failure to toggle the CLRDOG bit
38 Extensible Single Board Computer/Controller User's Manual
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