Read-Modify-Write; Dmac - Performance Computer PT-VME151A User Manual

3
Section FUNCTIONAL DESCRIPTION
!

Read-Modify-Write

DMAC

The DMA Controller in the DARF64 can transfer data between the VMEbus and DRAM or EPAK
memory in several different address and data modes. It is controlled through four internal registers:
DMA Local Address Register, DMA VMEbus Address Register, DMA Transfer Count Register,
and the DARF64 Mode Control Register.
The DMAC can be programmed to use A64, A32, or A24 addressing, in supervisor or nonprivilege
mode. The upper 32 bits of the A64 address are static and provided by the Master A64 Address
Register. The lower 32 bits of the A64 address and A32 or A24 addresses are provided by the DMA
VMEbus Address Register.
Data transfers can be programmed to occur in discreet (D32/D16), block (D32BLT/D16BLT), or
multiplexed block (D64MBLT) mode. The DMA Transfer Count Register allows up to 4 megabytes
of data to be transferred. The hardware automatically releases Address Strobe on the proper bound-
aries on the local and VMEbus.
To further improve transfer rates the PT-VME151A supports "Burst Mode" transfers from the
DARF64 on the local bus. Burst lengths of 4, 8, 16, or 32 longwords can be programmed using the
BLEN field of the DARF64 Mode Control Register. Given 32 longword bursts and the 4-2-2-2...2
DRAM burst timing a maximum data transfer rate of 49.2 megabytes per second is achievable over
the local bus. The DMA Burst Enable (DMABEN) and FIFO Burst Enable (FIFOBEN) bits in the
36 Extensible Single Board Computer/Controller User's Manual
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
mode the FIFO is bypassed and the CPU waits for the VMEbus acquisition and transfer to take
place. All 68040 reads bypass the FIFO.
Access to the VMEbus address space by the 68040 CPU is through addresses 80000000h -
FFFFFFFFh. In order to access the full VMEbus address space the Page bit in the 151A System
Control Register defines VMEbus address bit 31. When the Page bit is 0, PT-VME151A
addresses 80000000h-FFFFFFFFh are mapped to VMEbus addresses 00000000h -
7FFFFFFFh. When the Page bit is 1, PT-VME151A addresses 80000000h-FFFFFFFFh are
mapped to VMEbus addresses 80000000h-FFFFFFFFh.
For CPU accesses the DARF64 splits 4 Gigabyte VMEbus address space into 32-128 megabyte
pages. Most pages are defined to be A32:D32, however selected ranges may define to be
A24:D32, A24:D16 and A16:D16 spaces.
CAUTION: When the CPU performs an access in the A16:D16 range, the DARF64 will
respond to the CPU as a 16 bit device, unlike the 68030, the 68040 will NOT split up the cycles
if necessary. Similarly, for references in the A24:D16 space.
A24:D32 and all A32 accesses allow 32 bit transfers from the 68040. The implied addressing
space and the CPU function codes determine the data or program, and supervisory or nonpriv-
ileged aspects of the Address Modifier code.
The DARF64 is capable of supporting single address Read-Modify-Write MC68040 instruc-
tions (TAS) across the VMEbus. The 68040 CAS and CAS2 instructions can require two
addresses during a "locked" operation, thus translating into a requirement for Address Strobe to
be asserted twice on the VMEbus while remaining "locked" in between. The VMEbus Specifi-
cation provides no mechanism for supporting this class of operations.