Software Watchdog Timer; Signal Descriptions; Programmer's Model - Motorola DragonBall MC68328 User Manual

6.2 SOFTWARE WATCHDOG TIMER

The software watchdog timer protects against system failures by providing a means to
escape from unexpected input conditions, external events, or programming errors. The third
16-bit timer block serves as a software watchdog timer for providing protection.
Once started, software must clear the software watchdog timer on a regular basis so that it
never reaches its time-out value. Upon reaching the time-out value, it is assumed that a sys-
tem failure has occurred, and the software-watchdog logic initiates a hardware reset of the
chip or a maskable interrupt to the CPU, depending on the force-interrupt (FI) control bit in
the watchdog control register (WCR).
The software watchdog timer uses the 32 kHz clock as the input to the prescaler. The pres-
caler circuitry divides the clock input by a fixed value of 8. The output of this prescaler cir-
cuitry is connected to the input of the 16-bit counter. The reference/compare register is a 16-
bit programmable register. The maximum value that can be programmed is 65535, i.e. FFFF
in hex.
The watchdog timer starts counting once it is activated by setting the enable bit in the control
/status register. The counter is locked after it starts running; it will be disabled and cleared
if and only if a software reset or external reset is asserted. Once the count reaches the ref-
erence value programmed in the reference register, either a maskable interrupt or a soft-
ware reset will be issued to the system, depending on the FI bit in the control/status register.
The counter asserts an internal output to the system-reset logic for an input clock cycle, i.e.
the 32 kHZ clock if the FI bit is clear. Otherwise, the maskable interrupt is asserted to the
CPU. In the case of an interrupt, the counter will continue to count. Both the interrupt and
counter will be cleared by writing into the counter.
The reset source bits (RS1-0) in the SCR are updated with the cause of the reset identified
as the software watchdog. Users can also check the reset-status bit in the watchdog timer
control/status register to identify the reset source.
The value of the software watchdog timer can be read at any time.

6.3 SIGNAL DESCRIPTIONS

TIN
This pin is the input to the timer and can be used in capture mode to latch the contents of
the free-running counter. It can also serve as the source of the clock to the prescaler.
TOUT
This pin is the output of the timer and can be programmed to toggle or pulse whenever a
"compare" event occurs.

6.4 PROGRAMMER'S MODEL

Users may modify the general-purpose timer registers at any time.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
Timer
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