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Table 6-7 Power Management Control/Status Register (PMCSR)
Field
Bits
Name
Power State 1:0
Power State 15:2
The offset for each register is listed as an offset from the beginning of the linked list item that is determined either from
the CAP_PTR (if Power Management is the first item in the list) or the NEXT_ITEM_PTR of the previous item in the list.
6.2.5
Capability Identifier: CAP_ID (Offset = 0)
The Capability Identifier, when read by system software as 01h, indicates that the data structure currently being pointed to
is the PCI Power Management data structure. Each function of a PCI device may have only one item in its capability list
with CAP_ID set to 01h.
Table 6-8 Capability Identifier (CAP_ID)
Bits
Default Value
07:00
01h
Figure 6-1, 'Linked List for Capabilities,"
location of the first item in the list. PCI Power Management registers have been stated as example in this list (although the
capabilities can be in any order).
•
The first byte of each entry is required to be the ID of that capability. The PCI Power Management capability has an
ID of 01h.
•
The next byte is a pointer giving an absolute offset in the functions PCI Configuration Space to the next item in the
list and must be DWORD aligned.
•
If there are no more entries in the list, the NEXT_ITEM_PTR must be set to 0 to indicate an end of the linked list.
Each capability can then have registers following the NEXT_ITEM_PTR.
The definition of these registers (including layout, size, and bit definitions) is specific to each capability. The PCI Power
Management Register Block is defined in
45732 AMD 780E Databook 3.10
6-4
Default
(Reset)
00
This field describes the power state of the graphics core.
States
00 = D0
01 = D1
10 = D2
11 = D3
0
These Read Only bits will return the clock status of each clock tree, generated inside the clock
block.
Read/
Write
Read Only
shows the implementation of the capabilities list. The CAP_PTR gives the
Figure 6-1, 'Linked List for Capabilities,"
Power Management for the Graphics Controller
Description
Function
Normal operation, no power savings enabled
Sleeping state 1:
Display is off
Host access to DRAM is allowed
Sleeping state 2
Display is off.
All engines are off.
Graphics core does not respond to host accesses to the frame buffer.
Everything, except Host Interface, is turned off.
This field, when set to 01h, identifies the linked list item as being the PCI Power
Management registers
Description
below.
© 2009 Advanced Micro Devices, Inc.
Proprietary
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