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A: Signal Descriptions
A.2
Coprocessor interface signals
The coprocessor interface signals are shown in Table A-2.
Name
EXTCPA
EXTCPB
EXTCPCLKEN
EXTCPDIN[31:0]
EXTCPDOUT[31:0]
CPnCPI
CPnOPC
CPTBIT
CPnTRANS
CPnMREQ
EXTCPDBE
A-2
Table A-2 Coprocessor interface signal descriptions
Type
Description
Input
External coprocessor absent.
This signal must be HIGH if no external coprocessor is present.
Input
External coprocessor busy.
Output
External coprocessor clock enable.
Output
External coprocessor data in.
Input
External coprocessor data out.
Output
Not coprocessor instruction.
When LOW, this signal indicates that the ARM720T processor is
executing a coprocessor instruction.
Output
Not opcode fetch.
When LOW, this signal indicates that the processor is fetching an
instruction from memory. When HIGH, data, if present, is being
transferred. This signal is used by the coprocessor to track the ARM
pipeline.
Output
Thumb state.
This signal, when HIGH, indicates that the processor is executing
the THUMB instruction set. When LOW, the processor is executing
the ARM instruction set.
Output
Not coprocessor translate.
When HIGH, the coprocessor interface is in a nonprivileged mode.
When LOW, the coprocessor interface is in a privileged mode.
The coprocessor samples this signal on every cycle when
determining the coprocessor response.
Output
Not coprocessor memory request.
Input
External coprocessor data bus enable.
This signal when HIGH, indicates that the coprocessor intends to
drive the coprocessor data bus, CPDATA. If the coprocessor
interface is not to be used then this signal must be tied LOW.
EPSON
ARM720T CORE CPU MANUAL
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