Figure 9-17 Debug Control And Status Register Structure - Epson ARM720T Core Cpu Manual

9: Debugging Your System
The structure of the debug control and status registers is shown in Figure 9-17.
Debug
control
register
TBIT
(from core)
TRANS[1]
(from core)
DBGACKI
(from core)
Bit 2
Bit 1
DBGRQ
(from ARM720T input)
Bit 0
DBGACKI
(from core)
9-42
+
+
+
+

Figure 9-17 Debug control and status register structure

Debug
status
register
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EPSON
Interrupt mask enable
(to core)
DBGRQI
(to core)
DBGACK
(to ARM720T processor
output)
ARM720T CORE CPU MANUAL